透過您的圖書館登入
IP:3.138.175.180
  • 學位論文

四位元每秒二十五億次取樣速率 快閃式類比數位轉換器

4-bit 2.5-GS/s Flash ADC in 0.18μm CMOS

指導教授 : 陳淳杰
若您是本文的作者,可授權文章由華藝線上圖書館中協助推廣。

摘要


在本篇論文實現一個四位元、每秒二十五億取樣速率的快閃式類比數位轉換器。設計平台則使用TSMC 0.18μm 1P6M CMOS製程。電源供應1.8V,功率消耗59.78mW。模擬結果顯示該快閃式數位類比轉換器在取樣速率每秒二十五億,輸入頻率1240.23MHz,SNDR可達到23.13dB,換算成ENOB為3.55bit。

並列摘要


In this paper, a Flash analog-to-digital converter with an 4-bit 2.5GS/s is implemented. Design platform is TSMC 0.18μm 1P6M CMOS process. The power consumption is 59.78mW at 1.8V power supply. The simulation results demonstrate that the proposed flash ADC achieves an SNDR of 23.13dB,which ENOB is 3.55bit at 2.5GS/s with a 1240.23MHz input frequency.

參考文獻


[1]R. Jacob Baker, Harry W. Li, and David E. Boyce., CMOS Circuit Design, Layout, and Simulation., Second Edition, New York: IEEE Press, 2002.
[2]P. Scholtens and M. Vertregt, “A 6-b 1.6-Gsample/s Flash ADC in 0.18-μm CMOS Using Averaging Termination,” IEEE. J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609,Dec.2002.
[3]S. Park, Y. Palaskas, A. Ravi, R. E. Bishop, and M. P. Flynn, “A 3.5GS/s 5-b Flash ADC in 90 nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., pp. 489-492, Sep. 2006.
[4]Chia-Nan Yeh and Yen-Tai, “A Novel Flash Analog-to-digital Converter,” Intermational Symposium on Circuits and Systems, pp. 2250-2253,2008.
[5]K. Uyttenhove, M. S. J. Steyaert, “A 1.8V 6Bit 1.3GHz Flash ADC in 0.25μm CMOS”, IEEE J. Solid-State Circuit, Vol.38, pp.1115~1122, Jul. 2003.

延伸閱讀