六位元每秒十億次取樣三十毫瓦功率消耗以90奈米製作之類比數位轉換器

A 6-bit 1-GS/s 30-mW ADC in 90-nm CMOS Technology

連原慶(Yuan-Ching Lien)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2007年)

https://doi.org/10.6342/NTU.2007.00606

摘要

在本論文中，以台積電90奈米先進製程實現了一個包含前置之追蹤保持電路取樣速率為每秒十億次六位元之子區段類比數位轉換器。此類比數位轉換器應用了在精細轉換器中的對摺式輸入、管線式運作、偏移量校正及數位錯誤修正等技巧。其輸入端電容量只有350 fF，使得它可以容易地被驅動。
操作在每秒十億次取樣速率時，超過1.1 GHz的等效解析度頻寬特性使得此類比數位轉換器能在奈奎斯特與子取樣頻率中操作。量測結果顯示，偏移量校正能將微分線性誤差由+1.78/－1.00 LSB修正為+0.35/－0.27 LSB。而積分線性分誤差由±2.67 LSB修正為±0.61 LSB。此類比數位轉換器能在低頻輸入訊號時得到5.5 bits的有效位元。在輸入訊號頻率高達1 GHz時，其有效位元仍大於5.2 bits。當輸入低頻至900 MHz訊號時，量測到的無雜訊動態範圍可達40 dB以上。操作在每秒十億次取樣速率時，此類比數位轉換器從1.2伏特的類比供應電壓及1.0伏特的數位供應電壓僅消耗30毫瓦之功率。其核心電路部分佔了0.18 mm2.

關鍵字

子區段 ； 類比數位轉換器 ； 對摺式輸入 ； 管線式運作 ； 偏移量校正

並列摘要

In this thsis, a 6-bit 1-GS/s subranging analog-to-digital converter (ADC) with fornt-end track-and-hold amplifiers (THAs) is implemented in TSMC 90-nm CMOS technology. This ADC incorporates folded input for the fine ADC as well as pipelined operation, offset calibration and digital correction techniques. The input capacitance of this ADC is only 350 fF, which makes it easily drivable.
Operating at 1 GS/s, a high effective resolution bandwidth (ERBW) above 1.1 GHz is obtained which allows it operates at both Nyquist rate and under sub-sampling. The measurement results show that the offset calibration improves the DNL from +1.78/－1.00 LSB to +0.35/－0.27 LSB, and the INL from ±2.67 LSB to ±0.61 LSB respectively. It achieves ENOB of 5.5 bits for low-frequency input, and greater than 5.2 bits up the 1-GHz input. The measured SFDR remains above 40 dB up to the 900-MHz input. It consumes only 30 mW from 1.2-V analog/1.0-V digital supplies at 1 GS/s. The active area is 0.18 mm2.

並列關鍵字

Subranging ； ADC ； Folded Input ； Pipelined Operation ； Offset Calibration

參考文獻

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