DSTTD 多天線系統下K-Best 檢測器之 硬體架構設計與實現

Hardware Architecture Design and Realization of the K-Best Detector for DSTTD MIMO Communication Systems

吳佳叡(Jia-Ruei Wu)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2012年)

摘要

有關於多天線輸入輸出(MIMO) 的技術, 近幾年來備受關注, 而雙重時空多
樣(DSTTD) 系統, 不僅擁有MIMO 系統的優點, 另外還能提供傳送端分集增益與
改善空間多工的增益, 且不增加系統總體的頻寬, 因此為一相當實用的技術。本論
文探討在此系統下訊號的檢測問題, 選擇K-Best 演算法來當做檢測的方式, 並利
用SE 列舉法與DSTTD 系統的特性, 對傳統的K-Best 演算法做進一步化簡的處
理。硬體的實現方面, 設定的環境是4 × 2的DSTTD 複數系統, 使用16-QAM 與
64-QAM 調變, K 值分別為4與8 , 並以18位元長度, 來代表運算的數值, 至於傳
送符元(symbol) 部分, 16-QAM 是以3位元表示而64-QAM 則是以4位元表示。架
構設計完畢以後, 根據排序方式的不同, 與能不能做參數調整, 一共分成三種不
同的架構, 接著再使用Xilinx ISE 12.2進行Verilog 程式的撰寫, 並以Matlab 程式
輔助驗證程式的正確性, 之後選擇Virtex 4系列中, 型號為xc4vlx100-12ff1148的
電路板合成(synthesis) 。在最後的合成的結果中, 三個架構的最大操作頻率依序為
81.562MHz 、80.223MHz 、62.806MHz 。
關鍵詞- MIMO , K-Best , 樹狀搜尋, 電路合成, DSTTD , SE 列舉法

關鍵字

電路合成 ； 雙重時空多樣 ； K-Best 檢測器

並列摘要

The wireless multiple-input multiple-output (MIMO) systems provide two kinds
of gains, spatial diversity gain and spatial multiplexing gain, for data transmission. A
practical system to achieve both the spatial diversity gain and multiplexing gain for 4
transmit antennas is the double space-time transmit diversity (DSTTD). In the DSTTD
systems, the maximum likelihood detector (MLD) is the optimal detector. The MLD
requires very high computational complexity; therefore, many suboptimal detectors are
developed. The suboptimalK-Best detector is a low-complexity tree search detector that
performs closely to the MLD. At each level of the tree, only K nodes with the smallest
partial Euclidean distance (PED) are retained. The K-Best detector is especially suitable
for hardware implementation, because of its possible parallel architecture. We design
the complex-valued K-Best hardware architecture for detecting 16-QAMsignal and 64-
QAM signal in the 4-by-2 DSTTD system. The parameter K is selected to be 4 and
8. Every 18 bits are used to represent a real number. Every 3 or 4 bits are used to
represent a 16- or 64-QAM symbol, respectively. The designed hardware is described
by Verilog code, is function verified by Xilinx ISE, and is synthesized according to
the xc4vlx100-12ff1148 FPGA board. Three architectures are designed. The synthesis
results reveal that designed K-Best architectures can work with maximum frequency
81.562MHz, 80.223MHz and 62.806MHz, respectively.
Keywords - MIMO, K-Best, tree search, synthesis, DSTTD, SE enumeration

並列關鍵字

Synthesis ； DSTTD ； K-Best detector

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