DSTTD多天線系統下以ZF和MMSE前置處理之樹狀搜尋檢測器之硬體架構設計與實現

Hardware Realization of the Tree Search DSTTD MIMO Detection with ZF and MMSE Preprocessing

閔敬元(Ching-Yuan Min)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2013年)

摘要

多天線輸入輸出(MIMO) 的技術，近幾年為通訊發展的主要目標。而雙重時空多樣(DSTTD)系統, 它保有了MIMO系統中，藉由多重傳輸的方式來加強傳輸速度及抗干擾性這項優點，更可以提供傳送端分集增益與改善空間多工的增益，且不增加系統總體的頻寬，實為一相當實用的技術。本論文探討在此系統和SDM系統下訊號的檢測問題，選擇K-Best和FSD演算法來當做檢測的方式，並使用ZF和MMSE的法則作前置處理來比較。其中ZF更利用了SE 列舉法對演算法做進一步化簡的處理。 硬體的實現方面，設定的環境是4 × 2的DSTTD和4 × 4的SDM複數系統，使用16-QAM 調變，K值為4，其中的運算數值更以18位元長度來代表。至於傳送符元(symbol)部分，因為所選的是16-QAM，所以數值只會有3、1、-1、-3四種可能，也因此只需要用3位元表示即可。架構設計完畢以後，根據演算法的不同和前置處理的方法不同，大致可分成四種不同的架構。接著再使用Xilinx ISE 12.2進行Verilog程式的撰寫，並以Matlab 程式輔助驗證程式的正確性，之後選擇Virtex 6系列中，型號為xc6vlx760-2ff1760的電路板合成(synthesis)。

關鍵字

數狀搜尋

並列摘要

There are two kinds of gains, spatial diversity gain and spatial multiplexing gain by the wireless multiple-input multiple-output (MIMO) systems. A practical system to achieve both the spatial diversity gain and multiplexing gain for 4 transmit antennas is the double space-time transmit diversity (DSTTD). The maximum likelihood detection (MLD) is the optimal detector for the system but it requires very high computational complexity; therefore, many sub-optimal detectors are developed. The sub-optimal K-Best and fixed sphere decoding (FSD) detector are two low-complexity tree search detectors that performs closely to the MLD. In this thesis, the K-Best and FSD for the DSTTD and spatial division multiplexing (SDM) MIMO systems are studied. Also, the two detection schemes with either zero-forcing (ZF) and minimum mean square error (MMSE) preprocessing are investigated. Note that when ZF preprocessing is used, fast Schnorr-Euchner enumeration to reduce the computational complexity is possible. Hardware architectures for detecting 16-QAM signal in the 4-by-2 DSTTD and 4-by-4 SDM systems are designed. The parameter K for the K-best detector is selected to be 4. Every 18 bits are used to represent a real number. Every 3 bits are used to represent a 16-QAM symbol because there are only lattice points 3, 1, -1, and -3 in the 16-QAM. There are four designed architectures with different preprocessing and detection schemes. The designed hardware architectures are described by Verilog code, is function verified by Xilinx ISE, and is synthesized according to the xc6vlx760-2ff1760 FPGA board.

並列關鍵字

tree-search

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