具有空時碼之多模式多天線-正交分頻多工系統之樹狀搜尋檢測器硬體架構設計與實現

Hardware Architecture Design and Implementation of the Tree Search Detection for the 3-Mode MIMO-OFDM System with Alamouti STBC

龍星佑(Shing-You Lung)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2014年)

摘要

在多天線 (MIMO)系統下,最大相似度檢測器 (maximum likelihood detector,MLD)為performance最好的檢測器,不過由於在硬體實作上複雜度過高,因此衍伸了許多可以降低硬體複雜度的演算法。在本論文使用的三種不同系統分別為SDM,Hybrid STBC 和DSTTD,其中Hybrid STBC 和DSTTD 在傳送端都具有Alamouti矩陣可以增加分集增益 (diversity gain),且不增加系統總體的頻寬,並且選擇ORVD (orthogonal real-valued decomposition)的方法將複數訊號模型轉為實數模型。至於檢測的方法,我們則是使用SSFE 演算法來實現,SSFE在performance與ML相差不大且在硬體複雜度與K-Best相比下降低了許多。在硬體實現方面,我們提出適用於2x2的SDM,3x2的Hybrid STBC和4x2的DSTTD三種系統的3-mode SSFE硬體架構,並使用64-QAM調變,m = [1 1 1 1 2 2 4 4],其中運算的數值以18位元長度來代表,因為64-QAM所以Symbol只會有-7、-5、-3、-1、1、3、5、7 ,所以傳送Symbol要以4位元表示,此3-mode的硬體架構能夠用同一套的硬體架構達成切換的目的,在架構設計完成後我們使用Xilinx 12.2進行Verilog程式的撰寫,並以Matlab程式輔助驗證程式的正確性,最後使用Design Compiler合成 (synthesis),在ASIC 合成的結果最大操作頻率為101.4MHz ,gate count為697.5K ,吞吐量(throughput)可以達到608.4Mbps,這樣的吞吐量可以滿足IEEE 802.11n的規格。

關鍵字

樹狀搜尋 ； 多天線

並列摘要

In the multiple-input multiple-output (MIMO) systems, the maximum likelihood detector(MLD) is the optimal detector. However, MLD requires very high computational complexity; therefore, many suboptimal detectors are developed in order to reduce the computational complexity. In this thesis, three different MIMO systems, including spatial division multiplexing (SDM), hybrid space-time block coding (STBC), and double
space-time transmit diversity (DSTTD), are considered. Both the hybrid STBC and DSTTD MIMO systems use Alamouti STBC at their transmitter side to provide diversity gains. The signal model to represent the MIMO systems are complex-valued, but they are converted to the real-valued signal model by the orthogonal value decomposition method. The selective spanning with fast enumeration (SSFE) detector, which performs nearly optimal as the maximum likelihood detector, is to be implemented for the studied MIMO systems. The proposed hardware architecture is designed to provide detection of 64-QAMsymbols for three differentMIMO transmissionmodes, including the 2-by2 SDM, 3-by-2 hybrid Alamouti STBC, and 4-by-2 DSTTD MIMO transmissions.Word length used to represent a real-valued number in the designed architecture is 18 bits. The architecture is a receiver to work for the detection for one of the three modes at a time. The designed hardware architecture is described by Verilog code,
is function verified by Xilinx ISE, and is synthesized by Design Compiler. The designed 3-mode architecture requires 115K gates and provides detection throughput rate 603Mbps, while operating at frequency 100.6MHz. This architecture can be used to detect IEEE 802.11n signals with two spatial streams of data.

並列關鍵字

Hybrid space time block code (Hybrid STBC) ； double space time transmit diversity (DSTTD) ； spatial diversity multiplexing (SDM) ； selective spanning with fast enumeration (SSFE) ； Alamouti ； orthogonal real valued decomposition (ORVD) ； Design Compiler

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