在SDM-MIMO多天線系統下高吞吐量之平行化多棵樹之軟性輸出搜尋檢測器硬體架構設計

Hardware Architecture Design of Parallel Multi-Tree Traversals to Provide High Throughput Soft-Output Detection in SDM-MIMO antenna System

武珈佑(Jia-You Wu)

指導教授 ： 劉宗憲

國立中正大學/工學院/通訊工程學系/碩士(2015年)

摘要

近來 hard-outputdetection的發展成熟,為了提高 information的BER,近幾年
衍生了許多 soft-output detection 的研究,提供 soft-output 資訊給後端的 decoder。
本論文為了提高 detecting throughput rate 選用 LORD (Layered ORthogonal lattice
Detector) 演算法作為 QR 分解為樹狀搜尋的前置處理,平行化多棵樹的軟性輸出
搜尋檢測器,在 SDM-MIMO 多天線系統下產生 soft-output 的資訊。因為通道矩
陣 H 使用 ORVD (orthogonal real-valued decomposition) 的方法將複數訊號模型轉
為實數模型,使得 R 矩陣具有兩兩一對的特性,有助於我們設計出一個可以同時
運算平行處理的硬體架構,並且為了有效的降低面積,此篇論文採用在樹狀搜尋的
最上層用一個 table 去選點然後下面的每一層都只保留一個最接近的子截點向下搜
尋,在 64QAM 下,我們保留36個 candidates,分成6個 clock cycle 去處理。在
架構設計完成後我們使用 Xilinx 12.2進行 Verilog 程式的撰寫,並以 Matlab 程式輔
助驗證程式的正確性,最後使用 Design Compiler 合成 (synthesis), 在 ASIC 合成的
結果最大操作頻率為100MHz,gate count 為550K,吞吐量 (throughput) 可以達到
400Mbps。

關鍵字

SDM ； ORVD ； 樹狀搜尋 ； 檢測器 ； 軟性輸出 ； 硬性輸出 ； 多天線 ； Design Compiler

並列摘要

In the multiple-input multiple-output (MIMO) systems, the maximum likelihood de-
tector (MLD) is the optimal detector. However, MLD requires very high computational
complexity; therefore, many suboptimal detectors are developed in order to reduce the
computational complexity. Recently, hard-output detecting is a well developed technol-
ogy. In order to improve the BER of information, a lot of newly derived researches of
soft-output provide back-end decoder with the soft-output information in recent years.
It is proposed in this thesis to reduce the tree traversal complexity of the Layered OR-
thogonal lattice Detector (LORD) to provide soft-output information in SDM-MIMO
system. To improve the implementation design, the studied detector adopts the orthog-
onalvaluedecomposition(ORVD)modeltorepresenttheMIMOsystemfromcomplex-
valued to real-valued system model. The R-matrix in this model has the paired entries.
And to further improve our implementation efficiency of area, we use a table to expand
child nosdes on the top layer of tree traversals, and expand only one closest-point child
node in remaining layers. For the scenario of four transmit and four receive anten-
nas, we expand 36 candidates for 64-QAM signals. Our architecture requires every 6
clock cycles to finish the tree traversal of an input received vector. The designed hard-
ware architecture was described by Verilog code, function-verified by Xilinx ISE, and
synthesized by Design Compiler. The designed architecture requires 550K gates and
provides detection throughput rate 400Mbps with working frequency 100MHz under
the TSMC 90 nm CMOS technology.

並列關鍵字

SDM ； ORVD ； tree search ； detector ； soft-output ； hard-output ； MIMO ； Design Compiler ； tree travelsal

參考文獻

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