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Reduced Power Consumption via Fewer Memory Accesses for Deep Packet Inspection
並列摘要
We propose a new mapping scheme for AC-DFA tries to be used in FPGA implementation of deep packet inspection (DPI). Our scheme greatly reduces number of memory accesses which are responsible for most of the power consumption in DPI. We vary strides in the construction of AC-DFA tries in such a way that the number of memory accesses is minimized without increasing the memory space. Compared with the state-of-the-art DPI architecture [3], our scheme shows 34% reduction in power consumption and 14% reduction in memory space.
被引用紀錄
葉哲儒（2014）。應用於三維反及閘式快閃記憶體之低漣漪電壓電荷幫浦系統設計〔碩士論文，國立清華大學〕。華藝線上圖書館。https://doi.org/10.6843/NTHU.2014.00653
Wu, Y. H. (2017). 結合基於單眼影像的車道線偵測與多層雷射的路緣偵測之可駕駛道路區域分析 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201703689
延伸閱讀
- Huang, Y. J. (2017). Architectures design and characterization of low power resistive random access memory [doctoral dissertation, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU201700727
- Huang, S. N. (2021). Hardware Implementation of High Efficiency Memory Controller Applied to High Bandwidth Memory [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU202104536
- 林俊穎（2004）。The solution to optimize the compatibility and performance of memory systems〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2004.10010
- Wang, P. H. (2017). Reducing Timing Discrepancy for Energy-Efficient On-Chip Memory Architectures with Low Voltage Processors [doctoral dissertation, National Chiao Tung University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0030-2212201712325200
- Lin, H. L. (2010). A Power Saving Cache Architecture for Multi-Core Processor [master's thesis, Tatung University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0081-3001201315110218