應用於高頻寬記憶體之高效率記憶體控制器硬體實現

Hardware Implementation of High Efficiency Memory Controller Applied to High Bandwidth Memory

黃紹農(Shao-Nung Huang)

指導教授 ： 李致毅

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202104536

摘要

近年來，區塊鏈技術的發展及運用成為人們廣為討論的一個議題，例如加密貨幣就是一種利用區塊鏈技術來實現去中心化的記帳方式。為了保護加密貨幣系統，中本聰先生設計了工作量證明(PoW)，透過獎勵提供加密算力者來保障貨幣的安全及穩定。從一開始的使用CPU來提供算力，接著到GPU、FPGA及ASIC，人們不斷找尋一個最省能源但卻能提供最大運算能力的方式。
ASIC挖礦晶片透過運算優化及平行運算來達到低功耗且高算力。但當某方持有過大的算力時就會失去去中心化的優點，導致帳本資料有可能會被竄改。為了對抗ASIC造成的算力壟斷問題，許多幣方從挖礦的演算法開始著手。本篇論文就舉乙太坊為例，乙太坊的挖礦演算法叫做Ethash，透過大量的隨機查表來加重記憶體附載，使瓶頸從運算速度轉移到記憶體頻寬來抵制ASIC。
本論文使用了Xilinx的U50 Accelerator Card來硬體實現Ethash演算法，主要針對此FPGA上的HBM(high bandwidth memory)來進行記憶體控制器的設計優化。本論文著重於如何最大運用HBM的頻寬來提升算力，並在有限的硬體資源內實現此演算法。
在此FPGA上合成結果頻率可以穩定操作在450MHz且記憶體頻寬使用率達89%，並可以利用DRP(Dynamic Reconfig)來進行動態調整頻率，使系統可以超頻運作在560MHz來更提升算力。

關鍵字

區塊鏈 ； 加密貨幣 ； Ethash ； FPGA 硬體實現 ； 頻寬使用率 ； 動態調頻

並列摘要

In recent years, the development and application of blockchain technology has become a widely discussed topic. For example, cryptocurrency is a decentralized accounting method that uses blockchain technology. In order to protect the cryptocurrency system, Mr. Nakamoto designed Proof of Work (PoW) to ensure the security and stability of the currency by rewarding those who provide cryptographic hash rate. From the beginning of using CPU to provide hash rate, then to GPU, FPGA and ASIC, people are constantly looking for a way that can provide maximum hash rate but save power.
ASIC mining chips achieve low power consumption but high hash rate through computational optimization and parallel operations. However, when a certain person holds too much hash rate, it will lose the advantages of decentralization, resulting in the possibility of falsification of ledger data. In order to combat the monopoly of hash rate caused by ASICs, many cryptocurrencies start from mining algorithms. This thesis takes Ethereum as an example, the mining algorithm of Ethereum is called Ethash, which uses a large number of random look-up tables to increase the memory loading, so that the bottleneck shifts from the computing speed to the memory bandwidth to resist ASIC.
This thesis uses Xilinx's U50 Accelerator Card to implement the Ethash in hardware, and is mainly aimed at the HBM (high bandwidth memory) on the FPGA to optimize the memory controller. This thesis focuses on how to maximize the HBM memory bandwidth utilization rate to increase hash rate and implement this algorithm within limited hardware resources.
The resultant frequency on this FPGA can operate stably at 450MHz and the memory bandwidth utilization rate reaches 89%. Through DRP (Dynamic Reconfigure Port) that can be used to dynamically adjust the frequency, the system can be overclocked to operate at 560MHz to increase hash rate.

並列關鍵字

blockchain ； cryptocurrency ； Ethash ； FPGA hardware design and implementation ； bandwidth utilization rate ； dynamic reconfigure port

參考文獻

[1] Hongjun Wu, “The Hash Function JH”, 16 January. 2011

[2] Guido BERTONI and Joan DAEMEN and Michaael PEETERS and Gilles VAN ASSCHE, “The Keccak reference”, January 14. 2011

[3] Danilo Gligoroski and Vlastimil Klima and Svein Johan Knapskog and Mohamed El-Hadedy and Jørn Amundsen and Stig Frode Mjølsnes, “Cryptographic Hash Function - BLUE MIDNIGHT WISH “, September. 2009

[4] Christophe De Canni`ere and Hisayoshi Sato, Dai Watanabe, “Hash Function Luffa “, October 31. 2008

[5] Shay Gueron and Simon Johnson and Jesse Walker, “SHA-512/256 “, October 28. 2008