- 期刊
頻寬最佳化硬體設計於移動補償之記憶體存取
Bandwidth Optimized Hardware Design for Motion Compensation Memory Access
摘要
本文提出一個最佳化的記憶體資料排列架構，能夠有效地減少記憶體的存取。根據演算法的運算結果，此架構可以減少AMBA AHB發出的需求訊號次數，以每個8×8的運算區塊而言，所減少的需求次數可以由10次減低至8次。與一般常見的傳統架構相比較之下，本文所提出的架構，在外部記憶體的存取次數的減少率而言，減少率分別約為19.8%（單位是每個8×8的運算區塊，而AMBAAHB的讀取延遲時間為20個時脈週期），和11.7%（單位是每個16×16的運算區塊，而AMBA AHB的讀取延遲時間為20個時脈週期）。在本文中，亦有提出讀取延遲時間與節省記憶體頻寬的關係比較表，結果顯示。當AMBA AHB所需的讀取延遲時間越高，則本文所提出的架構跟一般傳統常見的架構比較下，可以節省更多的記憶體頻寬。
並列摘要
A novel optimization strategy to efficiently reduce memory access data cycles is proposed, and also evaluated in an H.264/AVC design. The proposed strategy reduces the AMBA AHB requests from 10 to 8 times for each 8×8 block, by a sequential order memory allocation scheme. Compared to the traditional schemes, the proposed scheme can reduce the cycles for external memory access up to 19.8% (for each 8×8 block, AMBA AHB read latency is 20 cycles), and 11.7% (for each 16×16 block under the same latency). The relationship between latency and bandwidth saving is also provided. As a result, when the AMBA AHB latency is getting higher, the proposed scheme could save much more bandwidth.
延伸閱讀
- Huang, S. N. (2021). 應用於高頻寬記憶體之高效率記憶體控制器硬體實現 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU202104536
- 蔡承祐（2008）。草稿記憶體使用率動態最佳化之軟硬體整合設計〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2008.01148
- 羅崑崙、吳明學、陳振岸、陳宜文、白炳川（2014）。寬輸入輸出動態隨機存取記憶體之內建自我測試架構設計。電腦與通訊，(157)，70-78。https://www.airitilibrary.com/Article/Detail?DocID=1019391x-201406-201407020013-201407020013-70-78
- 林俊穎（2004）。記憶裝置效能及相容性之最佳化〔碩士論文，國立臺灣大學〕。華藝線上圖書館。https://doi.org/10.6342/NTU.2004.10010
- Zhang, L. W. (2016). A Reliability-aware Write Termination Scheme for Resistive Random Access Memory [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-1603201711075244