Wang, P. H. (2017). 時間落差消除以實現低電壓處理器中高能源效率之晶片內建記憶體 [doctoral dissertation, National Chiao Tung University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0030-2212201712325200
Lai, M. W. (2022). 探索並拓展軟體事務性記憶體的可排程性以增進其效能 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU202201972
Shen, R. C. (2012). 低功率預先計算為基礎的內容可定址記憶體之設計預估方法 [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2012.10791