近年來電子產品朝向高速度與高密度化發展,使得電路設計皆以低操作電壓、低功率來進行設計,造成電源輸送系統(Power Delivery System, PDS)容易受輸入訊號耦合到電源平面的影響,使電源產生波動不穩定的雜訊,進而使輸出訊號錯誤,更甚者將使整個系統不能正常工作,其中同步切換雜訊(Simultaneous Switching Noise, SSN)影響電源系統最為嚴重;衍生出電源完整性(Power Integrity, PI)的問題,然而一般在抑制同步切換雜訊是使用去耦合電容,但是此方式並不能有效降低雜訊,因此我們提出一套方法論來建構一個抑制雜訊的增強模組以提高電源完整性,當傳統IBIS 模型以此方法論來加上去耦合電容和增強模組時,在抑制同步切換雜訊的程度上比使用去耦合電容方式提高58.3%、比HSPICE模型提高59.8%,也比傳統IBIS模型提高73.2%,以此效益提供給IC或IC系統設計者以增進IC本身抗同步切換雜訊之能力。
Modern electronics products must have improved characteristics, including high-speed, high-density, and lower-voltage operations. With such designs, the power-delivery system is affected by the input noise and becomes unstable. Simultaneous switching noise is a major factor that interferes with power integrity. In this letter, we propose a novel design based on an enhanced I/O buffer information specification mode that effectively reduces the noise by over 58.3, 59.8, and 73.2% compared with the traditional de-coupling capacitor, HSpice, and IBIS model methods, respectively.