基於IBIS模型評估同步切換雜訊與基於VHDL實現非同步電路之設計方法研究

The Study of Design Methodologies for Evaluating Simultaneous Switching Noise based on IBIS Models and for Implementing Asynchronous Circuits based on VHDL

譚巽言(Sun-Yen Tan)

指導教授 ： 孫卓勳 ； 黃文增

國立臺北科技大學/電資學院/電腦與通訊研究所/博士(2010年)

摘要

越來越多的電子產品要求在高速度的條件下工作，再加上電子產品之開發朝向高密度微小化的趨勢，且須具備低功率消耗及低電壓的工作條件。由於電源傳送系統（power-delivery system, PDS）會因輸入的雜訊影響而使電源系統工作不穩定，而內部緩衝器同時動作產生同步切換雜訊 (simultaneous switching noise, SSN) 是衍生電源完整性問題 (power integrity, PI) 的主要因素。
同步切換雜訊已成為嚴重問題，而必須確保邏輯狀態的上升與下降時間內電源系統的穩定性。傳統設計是使用去耦合電容（decoupling capacitors）來降低同步切換雜訊；雖然使用去耦合電容並不能有效的降低同步切換雜訊，但該方法仍被使用在HSPICE（HP Simulation Program with Integrated Circuit Emphasis）模型中，以降低同步切換雜訊。當系統工作在高頻時，這些去耦合電容會變為等效串聯電感，失去降低同步切換雜訊之作用。
具增強模組的IBIS（I/O buffer information specification）模型可以有效地解決同步切換雜訊無法降低的問題，實驗結果顯示：具增強模組的IBIS模型同時使用去耦合電容時，降低同步切換雜訊的效能，較使用傳統IBIS模型提升73.2%；較使用傳統去耦合電容方法提升58.3%；較只使用增強模組的IBIS模型方法提升25.7%；較使用HSPICE方法提升59.8%；實驗結果並呈現：具增強模組的D-IBIS (differential I/O buffer information specification) 模型同時使用去耦合電容時，降低同步切換雜訊的效能，較使用其他方法提升40－64%。
本論文提出一種簡單直接的方法，可從行為方式建模VHDL描述合成出結構化方式建模VHDL描述之非同步式電路 (asynchronous circuit)，是一種使用微管線 (micropipeline) 操作模式的非同步式電路型式，此項技術已被應用於開發非同步式微處理機 (microprocessor)。本論文提出之研究工作，顯示出VHDL可適用於描述微管線系統 (micropipelined systems) 行為，並揭示二相 (2-phase) 與四相 (4-phase) 電路實現的電晶體數量、速度及能量之實驗數據比較。整體系統之計算可以看成是一個計算方塊與微管線栓鎖器 (micropipelined latches)，此一簡單架構有助於設計者使用VHDL模擬器，儘早對一個抽象系统評估其行為是否符合期望。
合成器能夠同時產生二相與四相微管線電路之結構化方式建模VHDL及Verilog描述；本論文並以VHDL提出二相與四相微管線電路之比較，並針對各種不同的微管線架構之模擬，提出一些洞察結果。若是將二相微管線電路之計算分成幾個階段 (stages)，可使得電路之速度提升；但是，將四相微管線電路之計算分成幾個階段 (stages)，電路速度則不會有太多的提升。
合成之電路可利用Cadence設計環境，產出電路圖及進行後續之佈局作業，本論文提出一些測試實例，呈現合成器之操作實況，並呈現使用TimeMill之佈局後模擬結果。總之，本項研究建立了一個可以利用標準硬體描述語言VHDL研發微管線操作模式非同步式電路之設計環境。

關鍵字

同步切換雜訊 ； 電源傳送系統 ； 電源完整性 ； 差分輸出入緩衝器資訊詳述模型 ； HP積體電路重點模擬程式 ； 去耦合電容 ； 輸出入緩衝器資訊詳述模型 (IBIS) ； 高頻低阻抗 (HFLI) 電路 ； 非同步式電路 ； 微管線電路 ； 非常高速積體電路描述語言 (VHDL) ； 合成

並列摘要

Electronic products increasingly require high speed, high density, and low-voltage operation. The power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. SSN has become a serious issue that must be addressed to ensure system stability during the short rise- and fall-times of the logic transient states. Most traditional designs have generally used decoupling capacitors to reduce SSN. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been used in the HP Simulation Program with Integrated Circuit Emphasis (HSPICE) model for reducing SSN. These capacitors become equivalent series inductances when the system operates at high frequencies. It works against reducing SSN. Therefore, the enhanced I/O buffer information specification (IBIS) model which is able to effectively alleviate the problem of SSN using an evaluation based on the enhanced IBIS model with decoupling capacitors and a high-frequency low-impendence circuit is required to employ. The experiments show that the new method can reduce noise more than 73.2%, 58.3%, 25.7%, and 59.8% comparing with other methodologies including IBIS, traditional decoupling capacitors, IBIS with a high-frequency low-impendence circuit, and HSPICE, respectively.
The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. A novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit is applied. The experiments show that the new method can reduce noise by about 40－64% comparing with traditional design methodologies.
This thesis presents a straightforward approach for synthesizing a structural VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on micropipelines, a style used to develop asynchronous microprocessors. The work presented in this thesis demonstrates that VHDL can be used to describe the behaviour of micropipelined systems. It also shows a comparison of 2-phase and 4-phase implementations in transistor count, speed, and energy. At the high level the computations of a whole system can be treated as one computation block with micropipelined latches. This simple structure helps the designer to estimate the expected behaviour of an abstract system as early as possible using a VHDL simulator.
The synthesizer can produce 2-phase and 4-phase structural VHDL and Verilog micropipelines. A comparison of 4-phase and 2-phase micropipelines using VHDL is also presented. From the simulations of the various configurations some insight is obtained. By carefully partitioning the computations into several stages of a 2-phase micropipeline, the circuit will speed up. Carefully partitioning the computations into several stages of a 4-phase micropipeline will not give as much speed-up.
The synthesized circuits are taken through to schematics and layouts in the Cadence design environment. Some test examples are presented to show how the synthesizer works. Postlayout simulation using TimeMill is also presented in this thesis. In summary, a design environment for asynchronous circuits has been established based upon the micropipeline style and VHDL, a standard hardware description language.

並列關鍵字

Simultaneous switching noise (SSN) ； Power delivery system (PDS) ； Power integrity (PI) ； Differential I/O buffer information specification ； HP Simulation program with integrated circuit emphasis (HSPICE) ； Decoupling capacitors ； I/O buffer information specification (IBIS) ； High-frequency low-impedance (HFLI) circuit ； Asynchronous circuits ； Micropipelines ； VHDL ； Synthesis

參考文獻

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