基於加強式IBIS模型的同步切換雜訊之感知與防制設計

Noise-Aware and Prevention Design of Simultaneous Switching Noise Based on an Enhanced IBIS Model

周慶棟(Ching-Tung Chou)

指導教授 ： 黃文增博士

國立臺北科技大學/電資學院/電腦與通訊研究所/碩士(2007年)

https://doi.org/10.6841/NTUT.2007.00210

摘要

近年來電子產品已朝向高速度與高密度化發展，更進一步，電路設計皆以低操作電壓和低功率來進行設計，這些將造成電源輸送系統（Power Delivery System, PDS）容易受輸入訊號耦合到電源平面的影響，使電源產生不穩定的雜訊。其中同步切換雜訊是影響電源輸送系統的主因，此雜訊將造成電源完整性（Power Integrity, PI）的問題，最後，當雜訊超過容忍範圍，將會使輸出訊號產生錯誤動作，也即造成訊號完整性（Signal Integrity, SI ）的問題。一般是使用去耦合電容抑制同步切換雜訊，但是此方式無法有效降低雜訊。因此，我們提出一套有效法則來建構一個具有抑制雜訊的增強模組以提高電源輸送系統的完整性。當傳統IBIS模型以我們所提出方法論加上去耦合電容和增強模組時，在抑制同步切換雜訊的能力上分別比使用去耦合電容方式提高58.3%、比HSPICE模型提高59.8%，也比傳統IBIS模型提高73.2%。因此，我們的方法可提供給IC或系統設計者以增進其本身抗同步切換雜訊之能力。

關鍵字

電源輸送系統 ； 同步切換雜訊 ； 電源完整性 ； 訊號完整性 ； 輸出入緩衝器資訊詳述模型

並列摘要

Modern electronics products must have improved characteristics, including high-speed, high-density, lower-voltage, low-power consumption operations. With such designs, the power-delivery system (PDS) is affected by the input noise and then becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity (PI). Finally, when this noise excesses its tolerating range, it causes of the wrong operations of output signal, which is called the signal integrity (SI) issue. Generally, most traditional mechanisms have used decoupling capacitors to reduce SSN. Such designs cannot effectively reduce SSN. Therefore, we propose a novel noise-aware design, namely the enhanced IBIS model, to effectively reduce SSN and promote the stability of PI in this thesis. In this thesis, we propose a novel design based on an enhanced I/O buffer information specification mode to be designed in integrated circuit chips that effectively reduces the noise by over 58.3, 59.8, and 73.2% compared with the traditional de-coupling capacitor, HSpice, and IBIS model methods, respectively. Hence, our proposed module can be designed in IC chip and effectively to prevent SSN.

並列關鍵字

Power Delivery System (PDS) ； Simultaneous Switching Noise (SSN) ； Power Integrity (PI) ； Signal Integrity (SI) ； IBIS (I/O Buffer Information Specification)

參考文獻

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