Study and Design of Low-Power CMOS Double Edge-Triggered Flip-Flop Circuit

低功率CMOS雙邊緣觸發正反器的研究與設計

余建政(Chien-Cheng Yu)

《修平學報》 28期 (2014/03) Pp. 55-65

摘要

在CMOS超大型積體電路設計中，由於時脈頻率和晶片複雜度的持續增加，降低晶片功率損耗是必要的。時脈網路的功率損耗中，正反器所消耗的功率佔時脈網路功率損耗的絕大部分。因此，透過降低正反器的功率損耗達到降低晶片總功率損耗便顯得非常的重要。本文提出一種新型低功率損耗CMOS雙邊緣觸發正反器電路設計。在CMOS超大型積體電路設計中，可以透過功率損耗、傳遞延遲和功率延遲乘積（Power-DelayProduct; PDP）等參數來加以分析比較。通常，功率延遲乘積適用於低功率損耗可攜式系統。在本文中，使用TSMC 180nm的製程技術模擬，並與三篇先前之雙邊緣觸發正反器電路，針對電晶體個數、功率損耗和功率延遲乘積加以分析比較。根據模擬結果顯示，本文所提出之雙邊緣觸發正反器可以顯著地減少功率損耗。

關鍵字

雙邊緣觸發正反器 ； 低功率損耗 ； 功率延遲乘積 ； 單邊緣觸發正反器

並列摘要

Low-power techniques are essential in modern CMOS VLSI design due to the continuous increase of clock frequency and chip complexity. In many applications, the power consumption of the IC clock system, composed of flip-flops and a clock distribution network, is one of the most power consuming subsystem in a CMOS VLSI circuit. As a consequence, the reduction of flip-flops power consumption is a crucial factor in IC design.In this paper, a new double edge-triggered flip-flop (DETFF) is presented in which power consumption is reduced. Several metrics are available for analysis of CMOS VLSI circuits, such as power consumption, delay, and power-delay product (PDP). In general, a PDP based metric is appropriate for low power portable systems. This paper compares three previously published DETFFs together with our design for their transistor counts, power consumption, and power-delay product. HSPICE simulation results employing TSMC 180nm CMOS technology indicate the proposed flip-flop can reduce effectively power consumption up to 39.62% and decrease power-delay product up to 76.78% respectively, as compared to other DETFFs.

並列關鍵字

double edge-triggered flip-flop (DETFF) ； power consumption ； power-delay product (PDP) ； single edge-triggered flip-flop (SETFF)

參考文獻

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