A Frequency Synthesizer with Low Phase Noise in UHF RFID Reader Based on Sigma-Delta Modulation Fractional Frequency Phase-Locked Loop

Gang Chen

《電腦學刊》 31卷4期 (2020/08) Pp. 222-233

https://doi.org/10.3966/199115992020083104017

摘要

According to the frequency emission characteristics and related specifications of Ultra High Frequency (UHF) radio frequency identification (RFID), the RFID frequency synthesizer puts forward higher requirements on the noise and spurious suppression of the phase-locked loop. Its performance directly affects the sensitivity and stability of the receiver. How to design a high-performance and low-noise direct digital frequency synthesizer is a hot research topic in the industry. Firstly, the system design scheme of frequency synthesizer in UHF RFID reader based on sigma-delta modulation fractional frequency phase-locked loop is proposed. Secondly, the design advantages of digitization, large loop bandwidth, high precision and stability, are discussed. Thirdly, the generation source of phase noise is studied in detail, and the noise contribution of each component of the frequency synthesizer including signal source, loop filter, phase detector and charge pump, voltage controlled oscillator, ΣΔ modulator, etc. is simulated one by one. Finally, according to the most stringent ETSI EN 302 208-l emission spectrum specification of multiple radio frequency identification protocols, the frequency synthesizer phase noise requirement is less than -104dBc/Hz@200k Hz and -125dBc/Hz@1M Hz. And in this solution, experimental results show that the phase noise is only -116dBc/Hz@ 200k Hz and -132dBc/Hz@ 1M Hz, which not only meets the requirements of the specification, but also has a large margin space.

關鍵字

delta sigma modulator ； frequency synthesizer ； phase noise ； radio frequency identification (RFID) reader ； ultra-high frequency band (UHF)