以次取樣相位鎖定迴路架構為基礎且不具除法器之低雜訊除小數頻率合成器

本論文呈獻一個操作於2.3億赫茲、500千赫茲頻寬且不具除法器之頻率合成器架構，此架構運用最近被提出的次取樣相位鎖定迴路(sub-sampling phase-locked loop)和再量化三角積分調變器(re-quantized modulator)達成低頻寬內和低頻寬外雜訊，一個數位校正迴路(digital correlation loop)和動態單位相稱(dynamic element matching)被提出當作有效的方法降低非線性以至於此頻率合成器能達到極佳的特性。此頻率合成器利用藉由數位脈波寬度調變器(digital pulse-width modulator)次取樣壓控震盪器(VCO)輸出完成除小數的操作，由於次取樣相位偵測器(sub-sampling phase detector)的鎖定範圍被限制導致可能鎖定在參考頻率的整數倍上，所以一個頻率鎖定迴路(frequency-locked loop)被運用確保正確的操作，一個自動頻率控制(automatic frequency control)被提出去藉由控制電容陣列來拓展操作範圍。這個架構被執行在零點一八微米互補式金氧半製程所實現且其主要面積為0.75平方毫米。在1.8伏特的電源供應下扣除掉壓控震盪器緩衝器(VCO buffer)和輸入參考頻率緩衝器(input reference frequency buffer)總共消耗9.61毫安培，在2.3億赫茲操作下被量測的相位雜訊為-112 dBc/Hz和-134 dBc/Hz在相對於主頻率分別50千赫茲和10兆赫茲。在主頻上被積分的相位雜訊為266毫微微米的抖動量(被積分範圍為10千赫茲到30兆赫茲)，質量因數(figure-of-merit)為-239.1dB在被提出的不具除法器和低雜訊除小數頻率合成器。

關鍵字

次取樣相位鎖定迴路；不具除法器；低雜訊；除小數頻率合成器；三角積分調變器

並列摘要

This thesis presents a 2.3 GHz, 500 kHz bandwidth divider-less frequency synthesizer architecture that leverages a recently invented sub-sampling phase-locked loop (SSPLL) and a re-quantized modulator to achieve lower in-band and out-of-band noise. A digital correlation loop (DCL) and dynamic element matching (DEM) are proposed as an efficient method to reduce the non-linearity so that the synthesizer can achieve excellent performance. The synthesizer sub-samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. Because the sub-sampling phase detector (SSPD) has a limited locking range and may lock to any possible integer multiple of reference clock, a frequency-locked loop (FLL) is added to ensure proper operation. The automatic frequency control (AFC) is proposed to extend the operated range of VCO by capacitor array controlled. The prototype is implemented in a 0.18-µm 1P5M CMOS process and its active area occupies 0.75 mm2. Operating under 1.8V, the core parts, excluding the VCO buffer and the input reference frequency buffer, dissipate 9.61mA. Measured phase noise at 2.3GHz achieves -112dBc/Hz and -134dBc/Hz at 50 kHz and 10 MHz, respectively. Integrated phase noise at this carrier frequency yields 266 fs of jitter (measured from 10 kHz to 30 MHz). The figure-of-merit is -239.1dB on the proposed divider-less low-noise fractional-N synthesizer.

並列關鍵字

sub-sampling phase-locked loop ； divider-less ； low-noise ； fractional-N frequency synthesizers ； delta-sigma modulator

參考文獻

[1] G. E. Moore, “Cramming more components onto integrated circuits”, Electronics, vol. 38, no. 8, pp. 114-117, Apr. 1965.

[2] B. Muer and M. Steyaert, CMOS fractional-N synthesizers design for high spectral purity and monolithic integration. Norwell, MA: Kluwer, 2003.

[3] X. Gao, E. Klumperink, P. Geraedts, and B. Nauta, “Jitter analysis and a benchmarking figure-of-merit for phase-locked loops,” IEEE Trans. Circuits Syst. II, vol. 56, no. 2, pp. 117–121, Feb. 2009.

[4] M. Perrott, T. Tewksbury, and C. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 2048-2060, Dec. 1997.

[6] C. Durdodt, M. Friedrich, C. Grewing, M. Hammes, A. Hanke, S. Heinen, J. Oehm, D. Pham-Stabner, D. Seippel, D. Theil, S. Van Waasen, and E. Wag-Ner, “A low-IF RX two-point ΣΔ-modulation TX CMOS single-chip bluetooth solution,” IEEE Trans. Microw. Theory Tech., vol. 49, no. 9, pp. 1531-1537, Sept. 2001.

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以次取樣相位鎖定迴路架構為基礎且不具除法器之低雜訊除小數頻率合成器

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