具有次取樣內圈相位雜訊濾波器之鎖相迴路設計

The Design and Analysis of a Phase-Locked Loop with a Sub-Sampling Inner-Loop Phase Noise Filter

丁修賢(Hsiu-Hsien Ting)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201901240

摘要

本論文呈獻一個操作於52.5億赫茲，以環形振盪器為基礎之鎖相迴路，具有次取樣內圈相位雜訊濾波器，可以達到較小的抖動。本架構使用雜訊抑制的負回授系統。近年來，許多相位雜訊濾波器都使用壓控延遲線和延遲單元以萃取出雜訊的資訊。但是，這些壓控延遲線和延遲單元電路的雜訊，往往嚴重地影響電路的表現。此外，因為穩定度的緣故，鎖相迴路的頻寬被限制在參考頻率的十分之一。所以，我們提出了具有次取樣內圈相位雜訊濾波器，在此架構中，沒有任何壓控延遲線和延遲單元用來萃取雜訊的資訊。還可以將鎖相迴路的頻寬延伸至參考頻率的三分之一。
此濾波器使用次取樣相位偵測器對鎖相迴路的輸出做取樣，將相位誤差轉換為電壓誤差。並且使用電容來儲存此電壓誤差維持了些許週期。然後，次取樣電流泵將目前週期的電壓誤差與前一個週期電壓誤差做相減。並且產生了一個具有誤差資訊的電流到迴路濾波器以校正輸出相位。
此外，這個架構可以額外地產生出一個在左半平面的零點，因此我們可以將頻寬延伸到參考頻率的三分之一，且沒有任何穩定度的疑慮。藉由此具有次取樣內圈相位雜訊濾波器，不只環形振盪器的雜訊，甚至相位頻率偵測器、電流泵的雜訊都可以被抑制。這個架構執行在40奈米互補式金屬氧化物半導體的製程，在0.9伏特的電源供應下，消耗9.01毫瓦。鎖相迴路輸出方均根抖動從50千赫茲積分至10百萬赫茲為1.95 微微秒。

關鍵字

鎖相迴路 ； 延遲迴路 ； 次取樣相位偵測器 ； 雜訊抑制 ； 相位雜訊濾波器

並列摘要

This thesis presents a 5.25-GHz ring-oscillator (RO)-based PLL that achieves low jitter by using a sub-sampling inner-loop phase noise filter (PNF). A feedback noise cancellation is utilized. Recently, voltage-controlled delay lines (VCDLs) and delay cells are widely used to extract the error information in PNFs. However, the noise of VCDLs or delay cells always limits the performance significantly. In addition, PLL bandwidth is limited to one-tenth of the reference frequency for the stability consideration. As a result, we proposed a sub-sampling inner-loop PNF without any VCDLs and delay cells to extract error information, and the bandwidth of this work is also extended to about one-third of reference frequency.
It samples the PLL output, to obtain an error voltage corresponding to phase error by SSPD. Capacitors are used to hold the voltage error for some period of time. Then, SSCP compares the error of the current period with the previous periods’. Then, it produces a current, which is proportional to the error information, to loop filter (LPF) in order to calibrate the output phase.
Besides, this structure can produce an additional zero which is on the left-half plane, so the bandwidth can be extended to about one-third of reference frequency without the stability problem. By using a sub-sampling inner-loop PNF, not only VCO noise but also PFD/CP can be eliminated. Implemented in a 40-nm CMOS technology, it consumes 9.01 mW from a 0.9-V supply. The RMS PLL output jitter integrated from 50 kHz to 10 MHz is 1.95ps.

並列關鍵字

phase-locked loop (PLL) ； delay-locked loop (DLL) ； sub-sampling phase detector (SSPD) ； noise cancellation ； phase noise filter(PNF)

參考文獻

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[2] Zhiqiang Huang, Bingwei Jiang, and Howard C. Luong, “A 2.1-GHz Third-Order Cascaded PLL With Sub-Sampling DLL and Clock-Skew-Sampling Phase Detector”, IEEE Transactions on Circuit and System I: Regular Papers, vol. 65, no. 7, pp. 2118-2126, July 2018.

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