具頻率漂移補償功能之鎖相迴路設計與實現

The Design and Implementation of the Frequency-Drift-Compensated Phase-Locked Loop

謝正恩(Cheng-En Hsieh)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2019年)

https://doi.org/10.6342/NTU201901150

摘要

本論文的研究主題可分為兩個部分。第一部分是實現頻率漂移補償功能的鎖相迴路，第二部分提出另一類比數位轉換器做法用來降低補償器的溫度係數。
首先，振盪器中存在一個有損的電感電容槽，在溫度變異的環境下會產生頻率漂移的現象，若變動的頻率超過鎖相迴路的諧調範圍，此非理想效應將導致鎖相迴路脫離鎖定，以至於無法產生一個穩定的時脈。為了降低溫度對時脈產生器的影響，我們提出一種可偵測頻率漂移的補償電路，其組成為一個具有小面積與低功耗特性的六位元類比數位轉換器，藉由產生的數位碼來解析頻率對溫度的資訊，並依此補償振盪器的增益，達到修正頻率漂移的目的。本研究實現之鎖相迴路的量測平均溫度係數為2.43 ppm/°，量測相位雜訊在1 MHz的頻率偏移為-108.32 dBc/Hz，在10 MHz的頻率偏移為-130.26 dBc/Hz。量測的參考頻率突波為-65.15 dBc，總功率消耗為6.32 mW。補償器的面積僅占總面積的1.26%，傳統架構約占10~15%。相較於現有文獻，本研究達到小面積且低溫度係數。
為了更加改善鎖相迴路的溫度係數與溫度補償範圍，補償電路的解析度與電容槽單元必須提高。因此，我們設計了一個十位元解析度的類比數位轉換器。由於溫度變化的速度較慢，在既定的操作頻率下，可藉由降低供應電壓來減少功率消耗。然而，這導致類比電路的設計將會受限於電晶體增益降低、操作區改變以及電壓容許空間降低等影響。為了突破這些瓶頸，我們提出疊加倍壓裝置與時間軸比較器的解決方案，使得電路保持固有線性度且滿足十位元解析度。取樣頻率為5 kS/s的量測訊號雜訊比為54.57 dB，有效解析位元為8.77 bit，總功率消耗為15.9 nW，品質因數為7.3 fJ/conversion-step。

關鍵字

頻率漂移 ； 振盪器 ； 鎖相迴路 ； 溫度係數 ； 類比數位轉換器 ； 品質因數

並列摘要

This dissertation consists of two parts. The first part aims to design a frequency-drift-compensated (FDC) phase-locked loop (PLL). The second part implements a 10 bit analog-to-digital converter (ADC) which uses to increase the resolution of the frequency-drift compensator.
First, the lossy LC-tank of a voltage-controlled oscillator (VCO) will induce the frequency drift due to the temperature variations. If the drifting frequency is larger than the tuning range of an LC-VCO, the PLL will unlock and cannot be a stable clock generator. To sense the drifting frequency of the LC-VCO, a 6 bit successive-approximation-register (SAR) ADC is used due to its small area and low power characteristics. The FDC adjusts the capacitor banks of the LC-VCO to compensate the frequency drift owing the temperature variations. The average temperature coefficient (TC) is 2.43 ppm/°C from 20 °C to 100 °C. The measured phase noise of this PLL is -108.32 dBc/Hz and -130.26 dBc/Hz at the frequency offset of 1 and 10 MHz, respectively. The measured reference spur at 75 MHz offset is -65.15 dBc. The total power dissipation of this PLL is 6.32 mW. The compensator area of the previous arts always occupied 10~15% of the active area however this FDC used only 1.26% of the active area for the temperature compensation.
Second, increasing the resolution of the FDC and the number of the capacitor banks can improve the TC and the temperature compensation range of the PLL, respectively. Therefore, the ADC resolution is design to 10 bit. The power consumption can be decreased by reducing the supply voltage. However, the intrinsic gain, operation region, and headroom of transistors deteriorates analogy circuits due to a low supply voltage. To overcome the above issues, a double-boosted sampling switch and a supply-boosted time-domain comparator are proposed to decrease the on-resistance of the switches and improve the conversion time, respectively. This ADC achieves the measured SNDR of 54.57 dB, which exhibits an effective number of bit (ENOB) of 8.77 bit without missing code. The total power dissipation is 15.9 nW. A figure-of-merit (FOM) of 7.3fJ/conversion-step for this ADC is achieved.

並列關鍵字

frequency drift ； oscillator ； phase-locked loop ； temperature coefficient ； analog-to-digital converter ； figure-of-merit

參考文獻

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