利用動態相位誤差補償技巧之快速鎖定鎖相迴路

A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops

黃昱翔(Yu-Hsiang Huang)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.10553

摘要

本篇論文實現了一個快速鎖定的鎖相迴路。藉由我們所提出的方法，鎖相迴路於鎖定期間，其相位誤差的大小與極性會持續性地被偵測。接著利用動態改變除數的方式來補償所偵測到的相位誤差。由於在鎖定過程中，鎖相迴路都維持在一個較小的相位誤差。因此，鎖定時間可有效地縮短。除此之外，在此作品內加入了一個輔助性的充電幫浦，提供適當的電流給迴路濾波器以加快頻率的改變速度。此快速鎖定的方法實現於一個50億赫茲的鎖相迴路。使用台積電0.18深次微米製程，整個鎖相迴路操作在1.8-V共花費11mA電流。所量測到的鎖定時間為2us於40-kHz的迴路頻寬下。在53.4億赫茲下，相位雜訊於1-MHz頻率誤差下為-114.28 dBc/Hz，參考頻率突波於10-MHz頻率誤差下低於-70 dBc。

關鍵字

鎖相迴路 ； 快速鎖定 ； 相位補償 ； 頻率合成器

並列摘要

This thesis presents a fast-locking technique for phase-locked loops (PLLs). In the proposed technique, the polarity and magnitude of the phase error at the phase-frequency detector (PFD) input is continuously monitored during the locking process. The detected phase error is then coarsely compensated by dynamically changing the divide ratios. The proposed method allows the PLL to maintain a small phase error throughout the frequency acquisition process; thereby reducing settling time. To further enhance the locking speed, an auxiliary charge pump is applied to the loop filter during the fast-locking mode to facilitate a rapid frequency update.
The proposed technique is incorporated in the design of a 5-GHz PLL. Fabricated in the TSMC 0.18-μm CMOS technology, the whole PLL dissipates 11 mA from a 1.8-V supply. The measured settling time is about 2μs at a 40-kHz steady-state loop bandwidth. At 5.34 GHz, the phase noise measured at 1-MHz offset is -114.28 dBc/Hz, and the reference spurs at 10-MHz offset are lower than -70 dBc.

並列關鍵字

PLL ； fast-locking ； phase error compensation ； frequency synthesizer

參考文獻

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