具基於時間迴路濾波器之次取樣鎖相迴路設計

Design of Sub-Sampling Phase-Locked Loop with a Time-Based Loop Filter

陳宗盛(Tsung-Sheng Chen)

指導教授 ： 呂良鴻

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202100855

摘要

本論文以TSMC 180 nm CMOS製程實現操作在2.4 GHz基於環形振盪器的鎖相迴路。結合了一個次取樣與一個基於時間積分器的技術，首先藉由次取樣的特性，來降低鎖相迴路輸出的頻帶內相位雜訊，不過也因為次取樣的關係，使得迴路濾波器上對電容器的需求更大，為了避免額外面積的損耗與成本，透過基於時間積分器的技術，可以將傳統電容器替代為儲存相位之電流控制振盪器，因此可以省下大量的面積。
此晶片操作在1.8伏特的電源供應下，功率的消耗為10.1mW，其核心電路面積約為0.024mm2，當輸入參考頻率為150 MHz時，輸出頻率為2.4 GHz，在頻率偏移1 MHz的相位雜訊表現為-104.1 dBc/Hz，參考突波為-37.84 dBc。

關鍵字

鎖相迴路 ； 次取樣 ； 小面積 ； 電流控制振盪器

並列摘要

This thesis implements a phase-locked loop based on ring-oscillator operating at 2.4 GHz in a TSMC 180 nm CMOS process. It combines a sub-sampling and time-based integrator technology. First, the sub-sampling feature is used to reduce in-band phase noise. However, because of the sub-sampling characteristic, the demand for capacitor on the loop filter is even greater. In order to avoid the loss and cost of extra area, the traditional capacitor can be replaced by the current-controlled ring-oscillator for storing phase through based on time integrator technology, so a lot of area can be saved.
This chip is operated 1.8 V power supply, the power consumption is 10.1mW, its core circuit area is about 0.024mm2, when the input reference frequency is 150 MHz, the out-put frequency is 2.4 GHz. The phase noise performance is -104.1 dBc/Hz at 1-MHz fre-quency offset, and the reference spur is -37.84 dBc.

並列關鍵字

phase-locked loop (PLL) ； sub-sampling ； small area ； current-controlled ring-oscillator (CCRO)

參考文獻

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[5]Junheng Zhu, Romesh Kumar Nandwana, Guanghua Shu, Ahmed Elkholy, Seong Joong Kim, Pavan Kumar Hanumolu “A 0.0021 mm2 1.82 mW 2.2 GHz PLL Using Time-Based Integral Control in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp.8–20, Jan. 2017.