基於時域積分器之鎖相迴路與數位鎖相迴路之迴路增益最佳化

A Phase-Locked Loop Using a Single-Ring-Oscillator-Based Integrator and a Digital Phase-Locked Loop With Adaptive Loop Gain Controller

蘇冠宇(Guan-Yu Su)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201901129

摘要

這篇論文的主題主要分為兩個部分，第一部分實現了一個具背景頻率校正之基於時域積分器之鎖相迴路。利用單個時域積分器，頻寬內的相位雜訊以及功率效能均能提升；使用背景頻率校正方法可以使鎖相迴路容忍製程、供應電壓、溫度的變異。引進時序錯綜的方法可以讓參考突波有效下降。量測到的相位雜訊在距離主頻100 kHz、1 MHz、10 MHz下分別為-100 dBc/Hz、-108 dBc/Hz、-110 dBc/Hz。方均根值抖動量為1.5 ps。此鎖相迴路的有效面積與功耗分別為0.0011 mm2以及1.22 mW，雜訊的品質因數為-235.6 dB。
第二部分實現了一個數位鎖相迴路。提出的自動迴路增益校正電路使用頻譜平衡的方法，利用偵測數位相位頻路偵測器輸出的高頻與低頻的成分來調整迴路頻寬使得整體的數位鎖相迴路有最小的方均根雜訊。在沒有供應電壓雜訊的情況下，量測到的相位雜訊在距離主頻100 kHz、1 MHz、10 MHz下分別為-90 dBc/Hz、-95 dBc/Hz、-101 dBc/Hz，其方均根雜訊為3.64 ps。在有5 mVPP 及300 kHz的供應電壓雜訊下，使用提出的自動迴路增益電路可以使方均根雜訊值從8.5 ps降到5.1 ps。此數位鎖相迴路的面積與功耗分別為0.016 mm2以及1.5 mW。

關鍵字

鎖相迴路 ； 時域積分器 ； 頻率校正 ； 數位鎖相迴路 ； 自動迴路增益控制器 ； 雜訊最小化

並列摘要

This thesis consists of two parts. The first part implements a phase-locked loop (PLL) using a single-ring-oscillator-based integrator with background frequency calibration. By introducing the single-ring-oscillator-based integrator, the in-band phase noise and the power efficiency of the PLL are improved. With background frequency calibration, it allows this PLL to tolerate process, supply voltage, and temperature variations. Moreover, the reference spur will be improved by using timing orthogonal scheme. The measured phase noise is -100dBc/Hz, -108dBc/Hz and -110dBc/Hz at the offset frequencies of 100kHz, 1MHz, and 10MHz, respectively. The integrated root-mean-square jitter is 1.5ps and achieves a figure-of-merit of -235.6dB. This PLL is fabricated in 40-nm CMOS process which occupies an active area of 0.0011mm2. Its power consumption is 1.22mW from a 1V supply voltage.
The second part implements a digital phase-locked loop (DPLL) using the proposed adaptive loop gain controller (ALGC). The ALGC uses a spectrum-balancing technique detect the difference of the high-frequency and the low-frequency powers of the bang-bang phase-frequency detector. Then, the loop gain of the DPLL is adjusted to minimize the output root-mean-square (RMS) jitter. This DPLL is fabricated in 40-nm CMOS process and its active area is 0.016mm2. The power consumption of the DPLL is 1.5mW from a 1V supply voltage. Without the power supply noise, the measured phase noise is -90dBc/Hz, -95dBc/Hz and -101dBc/Hz at the offset frequency of 100kHz, 1MHz and 10MHz, respectively. The integrated RMS jitter is 3.64ps, which is translated to have a figure-of-merit of -227dB. With a 5mVPP and 300kHz sinusoidal power supply noise, the RMS jitter is reduce from 8.5ps to 5.1ps by using the proposed ALGC.

並列關鍵字

phase-locked loop ； time-based integrator ； frequency calibration ； digital phase-locked loop ； adaptive loop gain controller ； jitter minimization

參考文獻

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