以次取樣相位偵測器架構為基底之時脈與資料回復電路

A Sub-Sampling Based Phase Detector Clock and Data Recovery Circuit

劉恆瑞(Heng-Jui Liu)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202003477

摘要

在高速資料有線傳輸系統中，時脈與資料回復電路扮(CDR) 演極重要的 腳色。CDR 會萃取出輸入資料的資訊並將其還原進而去除在傳輸過程中的 抖動。CDR 可以看成一個迴授系統去校正資料輸入以及還原時脈的相位差， 而在傳統的CDR 架構中，像是鎖相迴路迴路為基底的CDR，需要相位偵測 器(PD)、充電汞(CP)、迴路濾波器、還有電壓控制震盪器(VCO)。 傳統上來說，Hogge 相位偵測器可以實現追鎖相位的功能，但它需要 多重相位的資訊。因此許多CDR 都需要使用環形電壓控制振盪器，然而 其較高的KVCO 將導致使用大的電容來降低頻寬已達成好的抖動量傳輸 (JTRAN)，此外在高速資料傳輸率的應用中，電流模式邏輯(CML) 將被使 用，它會消耗較大的靜態功率。 本篇論文提出了以次取樣為基底的相位偵測器(SSPD) 以在高資料傳輸 率的應用中達成低的功率消耗，此外SSPD 結合了迴路濾波器以及充電汞創 造了沒有主動電路的相位偵測路徑。此外藉由多重頻帶VCO 的設計，我們 完成一個晶片內濾波器。 量測到的回復時脈峰對峰值抖動量為78mU(15.6ps)，有效值抖動量為 10.5mU(2.1ps)，而在資料速率為5Gb/s 和PRBS length=10 的情形下，抖 動量忍受度在10M 赫茲的時>0.22UI。供應電壓0.9V 時功耗為5.6mW， 使用的技術為TSMC 40nm 製成，總面積為0.339mm2。

關鍵字

時脈與資料回復電路 ； 次取樣 ； 接收器

並列摘要

In high-speed wireline data communication systems, clock and data recovery (CDR) plays a significant role. The CDR circuits extract the input data information and retime it to remove the jitter during transmission. The CDR circuits can be viewed as a feedback control system that adjust the phase difference between the input data and recovery clock. In the conventional CDR structure , such as PLL-based CDR , it needs a phase detector (PD) , a charge pump (CP), a loop filter, and a voltage control oscillator (VCO). Conventionally, the Hogge PD can realize the phase tracking function, but it needs multi-phase information. So many CDR circuits use the ring VCO type to overcome it. However the high KVCO in ring VCO needs a large cap to decrease the Band-width (BW) for good jitter transfer (JTRAN). Otherwise in the high speed data rate application, the current mode logic (CML) should be used, and it also consume large static power. In this thesis, we propose a sub-sampling based phase detector (SSPD) to achieve the low power dissipation in high speed data rate application, also the SSPD combines the loop filter and CP creating a non-active circuit in the phase detection path. By the multi-band VCO design, we also finish an on chip loop filter design. The measured peak to peak jitter of recovery clock is 78mU(15.6ps) and the rms jitter is 10.5mU(2.1ps), and the measured jitter tolerance results >0.22UI @10MHz with 5Gb/s data rate and PRBS length=7, respectively. The power consumption is 6.2mW with 0.9V supply voltage. The chip is fabrite in the TSMC 40nm technology and the total area is 0.339mm2

並列關鍵字

Clock and data recovery ； CDR ； Sub-sampling ； RX ； Receiver

參考文獻

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