Efficient Realization of BCD Multipliers Using FPGAs

Khurshid, B., & Mir, R. N. (2015). High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs. International Journal of Reconfigurable Computing, 2015(), 32-47. https://doi.org/10.1155/2015/518272
石顏彰、簡宜興、許陳鑑、王偉彥（2016）。FPGA-Based Realization for Feature Extracting Simultaneous Localization and Mapping。健行學報，36(3)，55-73。https://www.airitilibrary.com/Article/Detail?DocID=P20121108003-201607-201608030008-201608030008-55-73
Kerkiz, N., Elchouemi, A., & Bouldin, D. (2010). Multi-FPGA Partitioning Method Based on Topological Levelization. Journal of Electrical and Computer Engineering, 2010(), 379-383. https://doi.org/10.1155/2010/709487
Vera, G. A., Pattichis, M., & Lyke, J. (2011). A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs. International Journal of Reconfigurable Computing, 2011(), 258-276. https://doi.org/10.1155/2011/518602
Pratt, B., Fuller, M., & Wirthlin, M. (2011). Reduced-Precision Redundancy on FPGAs. International Journal of Reconfigurable Computing, 2011(), 483-494. https://doi.org/10.1155/2011/897189