Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Chen, Y. H. (2014). A Robust and Design Flow Compatible Standard Cell Sizing Method for VLSI Circuit Performance Optimization [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2014.10016
Chiang, K. Y. (2015). Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2015.10255
Kuo, C. Y. (2012). Testing of TSV-induced Small Delay Faults for Three Dimensional Integrated Circuits [master's thesis, National Taiwan University]. Airiti Library. https://doi.org/10.6342/NTU.2012.03320
Liu, Y. L. (2008). An ACO-based Pattern Generation for Peak Power Estimation in VLSI Circuits [master's thesis, National Tsing Hua University]. Airiti Library. https://www.airitilibrary.com/Article/Detail?DocID=U0016-2002201314560085
Zhou, J., Tian, S., Yang, C., & Ren, X. (2014). Test Generation Algorithm for Fault Detection of Analog Circuits Based on Extreme Learning Machine. Computational Intelligence and Neuroscience, (2014), 506-516. https://doi.org/10.1155/2014/740838