A Low-Noise Low-Power and Small-Area CMOS Preamplifier for Neural Signal Recording

Zixuan Huang ； Tong Yang

《World Scientific Research Journal》 7卷1期 (2021/01) Pp. 346-357

https://doi.org/10.6911/WSRJ.202101_7(1).0044

摘要

This passage proposed a low-noise low-power and small-area CMOS preamplifier for neural signal recording. Although the neural signal recording application put forward a demanding requirement for the preamplifier that should have sufficient magnification, low noise, low power consumption and small area occupation, the proposed preamplifier successfully finds a benign tradeoff between them. Covering the frequency range of both Action Potential (AP) and Local Field Potential (LFP), the proposed preamplifier has a bandwidth from 2.67 Hz to 4.73 kHz with a mid-band-gain of 40.07dB. An enhanced folded cascode structure is adopted for sake of low power and low noise of which the most of the transistors are set in the subthreshold region to further cutdown the power. The MOS-bipolar pseudoresistor element is also applied to reject large dc offset while occupying very small area and decreasing the input-referred noise which is measured to be 1.56 μVrms while consuming 0.8 μW of power from a 1.8 V supply. The chip is built in a standard 0.18 μm CMOS process while consuming 0.017 mm2 of chip area not including the bias circuit.

關鍵字

Brain-machine interfaces ； Neural-recording amplifier ； Low-power low-noise design ； Subthreshold operation ； MOS-bipolar pseudoresistor

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