This chip is a frequency synthesizer that uses a reusable delay line. This chip uses TSMC 90nm process. The total area is about 1mm x 1mm, and core area is 0.18mm x 0.25mm. When the power supply is 1V, the maximum output of the delay locked loop is 800 MHz, and the reference spur is -30.2 dBc, power consumption is 12.2 mW.(Power including output buffer)