應用於腦波偵測與霍爾磁場感應之類比前端電路設計

隨著物聯網時代的來臨，智慧家庭、智慧城市帶來越來越多便利性。智慧家庭乃是連結了生活周遭的智慧產品，透過這些智慧產品的即時感測與相互連接，成就物聯網的時代。而這些感測電路的主要任務為將振幅極小且低頻的信號直接轉換為數位訊號，並維持訊號的完整度。同時，功耗、雜訊、解析度與晶片面積也是很重要的設計考量。本論文實作了兩個電路。第一個作品實作一個用於腦波偵測的低功耗與低雜訊類比前端電路。這個晶片實作於聯電180奈米製程。這個前端電路包括了一個低雜訊儀表放大器與可編程式儀表放大器，這兩個儀表放大器皆選用電容耦合式儀表放大器來達成低功耗的訴求。最後達到整體功耗3.24微瓦特(單一通道)，並且在0.5到400赫茲的頻寬下得到積分雜訊為1.7微伏特(方均根)，而雜訊效率比(NEF)則達到3.7。第二顆晶片實作了一個磁感測器之類比數位轉換器。此電路實作於台積電180奈米製程，包括了一個傳感器與讀取電路，在讀取電路的部分，我們將儀表放大器與類比數位轉換器合而為一進而節省面積，同時積分器使用比傳統電路還要面積高效的壓控震盪器來實現。此外，我們使用動態偏移補償技術來降低低頻的偏移電壓與閃爍雜訊。這個作品也使用了數位截波器來消除電流控制震盪器之間的不匹配，還有數位輔助偏移補償術來解決動態範圍的問題。此晶片核心面積僅0.25平方毫米，同時在150毫特斯拉輸入磁場下維持50 dB的信號與雜訊比(頻寬為2.5 kHz)，在品質因素方面達到FoMs = 121 dB及FoMw = 147 pJ/conv。

關鍵字

低功率；低雜訊；感測器；類比前端電路；腦波偵測；壓控震盪器；類比數位轉換器；磁感測器；數位截波器；數位輔助偏移補償

並列摘要

In this dissertation, two circuits are presented. The first one realizes a low-power and low-noise analog front-end circuit for EEG application. It is fabricated in UMC 180-nm process. The analog front-end (AFE) includes a low-noise instrumentation amplifier (LNA) followed by a programmable gain amplifier (PGA) to further increase the gain. Both LNA and PGA employ capacitively-coupled IA (CCIA) topology to achieve good power efficiency. This chip uses the architecture without chopper technique and achieves total power consumption 3.24 uW per channel. The integrated noise from 0.5 to 400 Hz is 1.7 uVrms. The noise efficiency factor (NEF) is 3.7. The second work implements an area-efficient voltage-controlled oscillator (VCO) based ADC for a Hall sensor system. It is fabricated in TSMC 180-nm process. A sensor interface circuit that consists of a transducer and a read-out circuit is realized. In the read-out circuit, we merge the IA together with ADC in order to achieve good area efficiency. Also, chopper technique / spinning current technique is added to suppress the flicker noise. This work proposes a digital chopper that solves the residual offset from CCO mismatches, and digital offset reduction loop (DORL) that deals with the dynamic range issue of the ADC. The core area of the circuit is 0.25 mm2. The SNR is 50 dB (with the bandwidth of 2.5 kHz) under 150 mT input magnetic field signal. The figure of merits (FoM) FoMs equals to 121 dB and FoMw is 147 pJ/conv.

並列關鍵字

Low-Power ； Low-Noise ； Sensor ； Analog Front-End (AFE) ； EEG Sensing ； Voltage-Controlled Oscillator ； Analog to Digital Converter (ADC) ； Hall Sensor ； Digital Chopper ； Digitally-Assisted Offset Trimming

參考文獻

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[4] C. C. Tu, Y. K. Wang, and T. H. Lin, "A 0.06 mm2 ± 50 mV Range −82dB THD Chopper VCO-Based Sensor Readout Circuit in 40nm CMOS," 2017 Symposium on VLSI Circuits, Kyoto, 2017, pp. C84-C85.

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應用於腦波偵測與霍爾磁場感應之類比前端電路設計

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