天文接收機之放大器和應用於5G通訊系統之可變增益低雜訊放大器的研究

Research of Amplifiers for Astronomical Receivers and Variable Gain Low Noise Amplifiers for 5G Mobile Communications

張楷儁(Kai-Chun Chang)

指導教授 ： 王暉

國立臺灣大學/電機資訊學院/電信工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200003

摘要

本論文提出了三個部分。第一部分是應用於無線電天文接收機的寬頻低雜訊放大器，使用65奈米互補式金屬氧化物半導體(CMOS)製程來設計。第二部分是應用於下個世代的無線電天文接收機的K頻段極低功耗的低雜訊放大器，使用90奈米互補式金屬氧化物半導體製程來設計。最後一部分是應用於毫米波第五代行動通訊28和38 GHz頻段的低相位變化可變增益低雜訊放大器，也是使用90奈米互補式金屬氧化物半導體製程來設計。
在第一部分，提出了一個使用65奈米CMOS的高增益、寬頻、且高線性度的低雜訊放大器。此電路採用了共源級架構以實現高增益且低雜訊。為了增加頻寬，輸入與級間網路採用了兩段式匹配網路。量測結果顯示本文提出的低雜訊放大器在32 GHz的頻率下達到20.1 dB的小訊號增益和25.2 GHz的3-dB頻寬，頻寬內有3.6 dB的平均雜訊指數。此外，在18 mW的功耗下，此電路輸出功率的增益1dB壓縮點(OP1dB)達到2.2 dBm，晶片面積為0.4 mm2。
在第二部分，呈現了一個使用90奈米CMOS實現的K頻段極低功耗低雜訊放大器。此電路使用了電流再利用的技術來達到增益提高，單端中和技術也被應用在這個電路。此外，電晶體使用了基極浮接的技術以提高整體增益。量測結果顯示此低雜訊放大器在26 GHz的頻率下有19.3 dB的小訊號增益和且3-dB頻寬達到4.2 GHz。雜訊指數部分，在26 GHz的頻率下有3.3 dB的雜訊指數且頻帶內的雜訊指數皆小於4 dB，且功率消耗為1.8毫瓦。
最後一部分，提出了一個同樣使用90奈米CMOS實現的低相位變化且寬頻的可變增益低雜訊放大器。為了有效提高增益且降低雜訊，此電路採用了閘源極變壓器回授技術來同時達到阻抗和雜訊匹配。此外，為了有效提高穩定度且不犧牲增益，汲源極變壓器回授中和穩定技術(neutralization)也被應用在此電路。相位補償方面，利用兩級電流控制架構(current-steering)並在輸出端建構電感式相位反向網路，藉由相反的相位趨勢來達到相位的補償，使得相位變化盡可能地降低。量測結果顯示此可變增益低雜訊放大器在9.8 dB的增益控制範圍下相位變化小於7.2°，3-dB頻寬包含26~30.5和33.8~40.6 GHz，且最高增益為21.4 dB並在36 GHz達到4.7 dB的雜訊指數，功率消耗為17.9 mW。相較於先前已發表的CMOS低相位變化的可變增益放大器，此顆電路達到了最高的效能指標，顯示了在5G高效率通訊系統中發展的潛力。

關鍵字

互補式金屬氧化物半導體 ； 低雜訊放大器 ； 可變增益放大器 ； 毫米波 ； 高速場效電晶體

並列摘要

This paper consists of three parts. The first part is a broadband low noise amplifier fabricated in 65-nm CMOS process for radio astronomical receivers. Another presents a K-band ultra-low-power low noise amplifier applied for next-generation radio astronomical receivers, fabricated in 90-nm CMOS process. The other proposes low phase variation variable gain low noise amplifier also fabricated in 90-nm CMOS process for the fifth-generation mobile networks at the frequency bands of 28/38 GHz.
In the first part, a high gain, wideband, and high linearity low noise amplifier (LNA) fabricated in 65-nm CMOS process is proposed. This circuit uses a common-source (CS) topology to achieve high gain and low noise. In order to increase the bandwidth, two-section matching networks for input and inter-stage are utilized. The proposed LNA achieves a 20.1-dB small signal gain with 25.2-GHz 3-dB bandwidth (17.7-42.9 GHz) at 32 GHz, and the average noise figure within 3-dB bandwidth around 3.6 dB. In addition, the circuit achieves an output 1-dB compression point (OP1dB) of 2.2 dBm under 18-mW PDC, and the chip area is 0.4 mm2.
In the second part, a K-band ultra-low power low noise amplifier (LNA) fabricated in 90-nm CMOS process is presented. To reduce power consumption effectively, a current- reuse technique is utilized. In order to increase the gain and the stability with limited power consumption, a single-ended neutralization technique is applied to the circuit. In addition, each transistor adopts body-floating technique to increase the overall gain. The proposed K-band LNA achieves a 19.3-dB small signal gain with 4.2-GHz 3-dB bandwidth (23.8-28 GHz), a noise figure of 3.3 dB at 26 GHz and within 3-dB bandwidth maintained around 4 dB with only 1.8-mW PDC.
In the last part, a broadband variable-gain low-noise amplifier (VGLNA) with low phase variation also in 90-nm CMOS technology is proposed. In order to increase the gain and reduce the noise figure, a gate-source transformer-feedback technique is adopted for simultaneous noise and input impedance matching. Besides, in order to improve the stability without sacrificing gain, a drain-source transformer-feedback neutralization technique is also applied to the circuit. In terms of phase compensation, the cascaded gain-boosting current steering VGA and a modified current steering VGA with the inductive phase-inversion network at the output are utilized, the phase variation can be compensated through the opposite phase trend. As a result, the phase variation can be reduced as much as possible. The proposed broadband VGLNA achieves the variation of the phase characteristic is less than 7.2° within 9.8 dB gain control range (GCR), and the 3-dB bandwidth covering from 26~30.5 and 33.8~40.6 GHz with peak gain of 21.4 dB. The noise figure is 4.7 dB at 36 GHz. The dc power consumption is 17.9 mW. Compared with all the previously published low phase variation CMOS VGAs, the proposed VGLNA features the highest figure-of-merit (FOM), which shows the potential for high data-rate 5G mobile communication systems.

並列關鍵字

CMOS ； Low noise amplifier ； Variable gain amplifier ； Millimeter-wave ； Field-effect transistor

參考文獻

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