應用於無線感測網路之微控制器設計

在老齡化的社會中，遠端照護將會是未來的重要需求。隨著半導體製程技術的進步，將數位電路、類比電路、以及高頻電路整合於系統單晶片中已經可行。系統單晶片可使無線感測網路感測節點的單價以及體積大幅降低，可適用於遠端照護之需求。我們利用台積電0.35μm Mixed-signal 2P4M CMOS 製程完成了一應用於無線感測節點之系統單晶片。其中包含了微控制器、類比數位轉換器、儀表放大器、轉阻放大器、類比多工器、ASK 發射器、OOK 接收器、電壓調節器以及微控制器之附屬電路包括石英震盪器和通電重置電路。整個晶片大小包含117 個ESD PAD 為3298*3637μm^2。為了整合現有之資源例如編譯器，微控制器部分選擇相容於標準8051 指令集，共有111 個指令。其核心部分為一五級流水線架構，可以達到每個核心時鐘周期即執行一個指令。一個分支預測電路被用以增加流水線之性能。它包含4096 位元組之程式記憶體，256 位元組之資料記憶體，7 個中斷源。另整合周邊電路包含兩個擁有硬體循環冗餘校驗模組之通用非同步收發傳輸器、除頻器、計時器等。微處理器之最高時脈為36MHz，最高性能為18MIPS。其功率消耗為1.172mA 當操作於4MHz。低功耗設計為感測節點之關鍵課題。數位電路部分我們利用時鍾門控電路技術以及時鐘多工器來降低功耗。類比以及高頻電路部分則利用含開關之電壓調節器來控制每一個區塊之電源開關，以達到降低功耗之目的。

關鍵字

微控制器；系統單晶片；無線感測網路；低功耗設計；流水線

並列摘要

Distance medical treatment will become an important issue in upcoming ageing society. As a result of the advancement of semiconductor manufacturing technology, it is possible to integrate wireless transceiver, sensors, amplifier and digital controller into one single chip. This is called a SOC (System‐on‐Chip) chip. Hardware cost and size of a WSN (Wireless Sensor Network) sensor node can be reduced substantially using SOC technology and suitable for distance medical treatment. We achieved a SOC chip for WSN sensor node using TSMC 0.35 μm Mixed‐signal 2P4M CMOS technology. It is composed of a microcontroller, an ADC (analog‐to‐digital convertor), an Instrument Amplifier, a trans‐impedance amplifier, an analog multiplexer, a ASK transmitter, an OOK receiver, 5 regulators, a crystal oscillator and power‐on‐reset circuit. Size of the SOC chip including 117 ESD PADs is 3298*3637μm^2 The microcontroller is fully compatible with common 8051 MCUs. It has 111 instructions. The core of the microcontroller is pipeline architecture with 5‐stages. An instruction can be executed in only one clock period. 4096 bytes program memory and 256 bytes data memory are embedded. Peripherals such as UART transceivers with hardware CRC module, clock‐divider, and timer are also implemented. Maximum clock frequency of the microcontroller is 36MHz (i.e. 18MIPS). Power consumption is 1.172mA when the chip operates at 4MHz. Lower power design is a critical issue for WSN sensor node. Clock‐gating technique and clock‐multiplexing are used to reduce power dissipation of digital circuits. Regulators with switches are used to reduce power dissipation of analog and RF circuits. Each analog / RF block can be turned on or off separately.

並列關鍵字

Microcontroller ； System on Chip ； Wireless sensor network ； Low power design ； Pipeline

參考文獻

[1.1] Warneke, B., and et al., Jan., 2001, "Smart Dust: Communicating with a Cubic-Millimeter Computer," IEEE-Computer, Vol. 34, no. 1, pp. 44-51.

[2.1] Keshab K. Parhi, “VLSI Digital Signal Processing Systems – Design and Implementation”, Wiley

[3.2] C51 Development Tools, http://www.keil.com/c51/

[3.6] Claire Burguiere, Christine Rochange, Pascal Sainrat, “A Case for Static Branch Prediction in Real-Time Systems”, IEEE RTCSA, 2005

[3.8] TI (Chipcon) CC1010 datasheet, http:// www.chipcon.com/

國際替代計量

應用於無線感測網路之微控制器設計

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