以統一式有限場處理單元為基礎的可動態重規劃之里德所羅門解碼器矽智財設計

Dynamically Reconfigurable Reed-Solomon Decoder IP Design Based on Unified Finite-Field Processing Element

游志強(Jih-Chiang Yeo)

指導教授 ： 吳安宇

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10030

摘要

里德所羅門 (Reed Solomon, RS) 碼是一種通道編碼技術，在錯誤更正與維護資料正確性上扮演著重要的角色。RS碼一直被廣泛地使用在各種不同的應用上。對於要求高資料傳輸率的系統，大部分的RS解碼器設計，都採用平行式資料處理架構來實現高速ASIC晶片。而對於某些較低速的應用，例如DVB-T等，則有人使用fine-grained 有限場處理單元 (processing element, PE) 搭配DSP core作為控制核心，可藉由改變處理單元的使用量來變換資料處理速率與動態功率消耗。近來，可動態重規劃 (dynamically reconfigurable) 的VLSI電路架構已漸漸受到重視，它可同時兼顧ASIC的高效能與DSP的高彈性。
在本論文中，我們設計了一個coarse-grained統一式有限場處理單元，並以此建構出一個可動態重規劃之RS解碼器。此解碼器比ASIC式設計擁有更高的應用彈性，以及比DSP式設計具有更高的處理效能。我們提出了Multi-Symbol-Sliced (MSS)資料流處理架構，可在不同的資料傳輸率與動態功率消耗之間做取捨(tradeoff)。對於一個使用m個PE的MSS解碼架構而言，可以被動態重規劃在1-PE、2-PE、…、(m/2)-PE與m-PE的操作模式，提供不同的資料傳輸率與動態功率消耗。
我們提供了一個4-PE的可動態重規劃RS解碼器作為設計原型(prototype design)。在不同操作模式下，可動態改變資料傳輸率與功率消耗，以適用於各種不同系統上。從佈局後NanoSim模擬的結果顯示，這樣一個可動態重規劃的RS解碼器在不同操作模式下，其資料傳輸率與動態功率消耗之間呈現正向線性關係，讓使用者得以在高傳輸率與低功率消耗之間作動態取捨。此解碼器在1-PE、2-PE與4-PE操作模式下，可提供140Mbps/18.91mW、280Mbps/28.77mW 與560Mbps/48.47mW的資料傳輸率/動態功率消耗。除此之外，使用gated clocking設計，我們可更進一步節省28 ~ 56%的功率消耗。

關鍵字

里德所羅門 ； 解碼 ； 重規劃 ； 動態 ； 有限場 ； 處理單元

並列摘要

Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, many RS decoders are implemented as dedicated ASICs based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, some RS decoders are implemented using fine-grained processing elements (PE) controlled by a programmable DSP core, which can provide high flexibility. Recently, the reconfigurable (RC) VLSI architectures become attractive since it can retain both flexibility and speed performance.
In this thesis, based on a new coarse-grained PE, we develop the dynamically reconfigurable RS decoding architecture, which provides better flexibility and higher performance than ASIC-type and DSP-type designs, respectively. We propose the Multi-Symbol-Sliced (MSS) data-path structure, which supports the tradeoff between the data throughput rate and the power consumption. We design one m-PE architecture based on a coarse-grained unified finite-field Processing Element (PE). The m-PE architecture can be dynamically reconfigured to operate in 1-PE, 2-PE, …, m/2-PE and m-PE modes, which can support various requirements of the data throughput rate and the energy efficiency. In addition, by using the gated-clocking scheme, we can enhance the power saving greatly.
We demonstrate a prototyping design using four processing elements, which can be dynamically reconfigured to operate in 1-PE, 2-PE and 4-PE mode with 140Mbps/18.91mW, 280Mbps/28.77mW and 560Mbps/48.47mW data throughput rate/power consumption, respectively.

並列關鍵字

Reed-Solomon ； decoder ； reconfigurable ； dynamically ； finite-field ； processing element

參考文獻

[1] S. Lin and D. J. Costello. Jr., Error Control Coding: Fundamentals and Applications, Englewood Cliffs, NJ: Prentice-Hall, 1983.

[2] Wicker and Bhargava, Reed-Solomon Codes and Their Applications, IEEE Press, 1994.

[3] I.S. Reed and G. Solomon, “Polynomial Codes over Certain Finite Fields,” J. Soc. Ind. Apple. Math. 8, pp. 200-204, June 1860.

[8] Hanho Lee, Meng-Lin Yu, and Leilei Song, “VLSI Design of Reed-Solomon Decoder Architectures,” IEEE ISCAS, pp. 705-708, May 2000.

[11] Jung H. Lee, Jaesung Lee, and Myung H. Sunwoo, “Design of Application-Specific Instructions and Hardware Accelerator for Reed-Solomon Codes,” EURASIP Journal on Applied Signal Processing, vol. 2003, no. 13, pp.1346-1354, Dec. 2003.