氧化物薄膜電晶體之材料與元件研究

Studies of Materials, Device Structures and Device Processing for Oxide Thin Film Transistors

吳承翰(Cheng-Han Wu)

指導教授 ： 吳忠幟

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10151

摘要

I

摘要
透明金屬氧化物半導體是由具有(n-1)d
10
ns 0 (n≧4)電子組態的重金屬陽離子
和氧結合而成。金屬氧化物半導體的傳導帶是取決於金屬的 s 軌域重疊，而 s 軌
域為球形對稱，因此不管在結晶態或非晶態都可以有良好的重疊及高載子遷移率。
金屬氧化物由於不需維持在結晶態，所以適合於低溫下沉積。且金屬氧化物常具
有高能隙，因此在可見光下是透明的。憑藉這些優點，以金屬氧化物半導體為材
料所製作的薄膜電晶體，有可能取代非晶矽成為下一代顯示技術的主流材料。
本論文主要探討兩種常見的金屬氧化物半導體，氧化銦鎵鋅及氧化鋅錫，研
究其薄膜特性並製作各種結構之薄膜電晶體。首先藉由控制不同氫含量的氮化矽
覆蓋在氧化銦鎵鋅上，可改變其下半導體層的導電率，並透過這個原理，在薄膜
電晶體的通道及汲極/源極上覆蓋不同氫含量的氮化矽，可成功地製作出自我對準
式上閘極氧化銦鎵鋅薄膜電晶體。
此外為了降低對貴金屬銦的需求，開發不含銦的金屬氧化物半導體氧化鋅錫
製程以求降低製作成本，是未來金屬氧化物半導體的一個有潛力的研究方向。我
們可利用完整的微影蝕刻製程，製作出下閘極共平面氧化鋅錫薄膜電晶體，並且
可藉由調整氧化鋅錫的沉積條件，來達到最佳化的元件特性。我們更進一步製作
了利用濕蝕刻製程的背面通道蝕刻結構製作的氧化鋅錫薄膜電晶體。濕蝕刻製程
的背面通道蝕刻結構是現階段顯示工業所偏好的元件結構，但受限於適當的蝕刻
液及蝕刻後續的修補處理，金屬氧化物薄膜電晶體在目前較難以濕蝕刻方式製作此種元件結構。我們開發出利用酸液蝕刻，以及電漿進行蝕刻後續處理，可成功
地製作出鉬/鋁電極的背面通道蝕刻結構之氧化鋅錫薄膜電晶體。本論文之研究，
對未來相關的金屬氧化物薄膜電晶體技術相信有所幫助。

關鍵字

氧化物半導體 ； 薄膜電晶體 ； 氧化銦鎵鋅 ； 氧化鋅錫 ； 自組裝製程 ； 背面通道蝕刻

並列摘要

III

Abstract
Transparent metal oxide semiconductors are composed of heavy metal cations
(HMCs) with electronic configuration of (n-1)d
10
ns
0
(n≧4). The conduction band of
metal oxide semiconductors is dominated by the overlap of spherical metal s orbitals,
and thus carriers can transport in the conduction band with high mobility in either the
single crystalline or the amorphous phase. Metal oxide semiconductors can adopt the
low-temperature or even room-temperature deposition technology since the crystalline
phase is not necessary. In addition, the bandgap of most oxide semiconductors are large
and thus are usually transparent in the visible range. With these merits, metal-oxide-
semiconductor based TFTs have the potential to replace a-Si TFTs in the display
technology.
Self-aligned techniques are often used in conventional CMOS and Si-based TFTs
due to various merits. This dissertation investigates the self-aligned coplanar top-gate
InGaZnO TFTs using PECVD a-SiNx:H patterned to have low hydrogen content in the
channel region and high hydrogen content in the source/drain region. After annealing to
induce hydrogen diffusion from a-SiNx:H into the oxide semiconductor, the
source/drain regions become more conductive and yet the channel region remains
suitable for TFT operation, yielding a working self-aligned TFT structure. Such
fabrication involves neither back-side exposure nor ion implantation, and thus may be compatible with the typical and cost-effective TFT manufacturing.
IGZO is the most studied oxide semiconductors, but it contains the relatively rare
In element, thus In-free Zinc-Tin oxide (ZTO) has high potential in the oxide TFT
technology. We demonstrated the bottom-gate ZTO thin film transistors fabricated on
glass substrates with fully photolithographic/etching processes and with completed
passivation. The ZTO active layer were deposited by RF sputtering with different
combinations of chamber pressure, rf power, and Ar/O 2 ratio during sputtering of ZTO, in
order to obtain optimized device performances.
The back-channel-etch (BCE) type TFT process is most compatible to the
conventional a-Si TFT industry, since the number of masks required can be minimized
and is easier to scale down the channel length, especially when compared with etch-stop
type TFTs. However, oxide TFTs with the conventional BCE processing have the issues
that the oxide layer on the film surface would be corroded or damaged in wet etching of
source/drain electrodes, leading to failure or leaky devices. To realize ZTO TFTs with
the BCE structure, we adopted a wet etchant that is less corrosive to ZTO and repaired
the damage of the ZTO surface by an in-situ plasma treatment. Also, we performed
various physical and chemical examinations of the influence of the wet etchant and the
plasma treatment on ZTO surface and explained the mechanisms.

並列關鍵字

Oxide semiconductors ； Thin-film transistor ； IGZO ； ZTO ； Self-aligned process ； Back-channel-etch

參考文獻

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