全比較器二階三角積分調變器於低溫多晶矽薄膜電晶體製程之設計

Design of Comparator-Based Switched-Capacitor Second-Order Sigma-Delta Modulator in Low-Temperature Poly-Silicon Thin-Film Transistor Technology

林湛斐(Chan-Fei Lin)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2008年)

https://doi.org/10.6342/NTU.2008.10065

摘要

隨著低溫多晶矽薄膜電晶體製程的發展，以往要由CMOS製程來實現的顯示器周邊電路，漸漸地可用低溫多晶矽薄膜電晶體來製作。終極目標是希望將整個系統全部整合進玻璃中，以達到節省顯示器製造成本的目的。在觸控式螢幕的應用中，需要一個高解析度但低轉換率的類比數位轉換器，去將感測器所產生的類比訊號轉換成數位訊號，以讓後端的數位信號處理器做更進一步的分析與處理。對此種應用來說，三角積分類比數位轉換器是最佳的選擇。
一個三角積分類比數位轉換器分成兩部分，前半部份為三角積分調變器，後半部份則為數位濾波器，而轉換器的效能一般來說是由調變器所決定。因此，本論文的目標是要在低溫多晶矽薄膜電晶體製程下去實現一個二階的三角積分調變器。在一開始會利用系統模擬去選擇出在調變器中兩個積分器各自的增益。
接下去會提出兩個電路技術去解決由低溫多晶矽薄膜電晶體製程的非理想效應所帶來的問題。首先，因為此製程的電晶體有嚴重的製程偏移和通道調變效應，所以本論文採用了全比較器切換電容技術來實現積分器以減輕這兩個效應所導致的問題。再來考量到的是低溫多晶矽薄膜電晶體的臨界電壓會隨著溫度、製程、晶片位置而有大量的漂移，這種漂移會使比較器產生一頗大的偏差電壓，使得積分器甚至調變器的效能受到影響，因此本論文將偏差電壓補償技術應用在全比較器積分器上，以期將偏差電壓對效能的影響降低。
在本論文最後，成功地採用前面所提出的具偏差電壓補償之全比較器切換電容積分器來實現出一個二階的三角積分調變器。在透過所提出責任週率調整技巧去解決高取樣率所導致電路不完全放電的問題後，當調變器運作在超取樣率為128時，於1.56-kHz的信號頻寬中，量測到的輸入動態範圍為69dB，且最佳信號對雜訊及失真比為65.6dB。

關鍵字

全比較器 ； 三角積分調變器 ； 低溫多晶矽 ； 薄膜電晶體

並列摘要

With the development of the low-temperature poly-silicon thin-film transistor (LTPS-TFT) process, the peripheral circuits of the display panel that are realized by CMOS process in the past can be gradually implemented by LTPS-TFT. The ultimate goal is to integrate the whole system on a panel (SoP). In touch panel applications, a high-resolution data converter with low conversion-rate is required to convert the analog sensor signals to the digital bit streams that can be processed by DSP. The best candidate for this kind of application is the sigma-delta (ΣΔ) analog-to-digital converters (ADCs).
In a ΣΔ ADC, the ΣΔ modulator dominates the performance of the whole ADC. Thus, this thesis focuses on the implementation of a second-order ΣΔ modulator in the LTPS-TFT technology. System-level simulations are firstly performed to select the four integrator gains in the modulator.
Two proposals of circuit techniques are used to solve the serious non-idealities in the LTPS-TFT technology. First, the comparator-based switched-capacitor (CBSC) technique is adopted to implement the integrators due to the severe process variations and channel-length modulation effect in the LTPS-TFT technology. Second, the offset-compensated circuit is added to the integrators since the threshold voltages of the LTPS TFTs are sensitive to process, temperature, and the location on the chip. This sensitivity induces large offset voltages in the comparators of the integrators.
Finally, the experimental modulator is realized by using the proposed offset-compensated CBSC integrators. With the help of the proposed duty-cycle control method, it has 69dB dynamic range and 65.6dB peak SNDR in 1.56-kHz signal bandwidth for oversampling ratio of 128.

並列關鍵字

CBSC ； sigma-delta modulator ； LTPS ； TFT

參考文獻

[2]A. W. Wang and K. C. Saraswat, “A strategy for modeling of variations due to grain size in polycrystalline thin-film transistors,” IEEE Trans. Electron Devices, vol. 47, pp. 1035-1043, May 2000.

[3]D. A. Johns and K. Martin, “Analog integrated circuit design,” John Wiley and Sons, Inc. 1997.

[4]M. Pelgrom, A. Duinmaijer, and A. Welbers, “Matching properties of MOS transistors,” IEEE Journal of Solid-State Circuits, vol. 24, pp. 1433-1439, Oct. 1989.

[5]T. Mizuno, J. Okamura, and A. Toriumi, “Experimental study of threshold voltage fluctuation due tostatistical variation of channel dopant number in MOSFET's,” IEEE Trans. Electron Devices, vol. 41, pp. 2216-2221, Nov. 1994.

[7]A. Tomozawa and H. Kaneko, “Companded delta modulation for telephone transmission,” IEEE Trans. Comm. Tech., vol. 16, pp. 149-157, Feb. 1968.