5G機器型態通訊下針對稀疏碼多工存取之訊息傳遞解碼器設計與晶片實現

Design and Chip Implementation of Message Passing Based Decoder for Sparse Code Multiple Access in 5G Machine Type Communications

林芷敬(Zhi-Jing Lin)

指導教授 ： 闕志達

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2021年)

https://doi.org/10.6342/NTU202102168

摘要

在大規模機器通訊(mMTC)場景中，有限的頻譜與低延遲、低成本的需求為一大技術瓶頸，非正交多工存取(NOMA)成為5G的一項關鍵技術。其中稀疏碼多工存取(SCMA)即為一個近年備受關注的候選方案，其具有低傳輸延遲和高頻譜效率的優點。稀疏碼多工存取(SCMA)能根據情境使用不同的碼簿與過載因子，但系統的過載因子上升的同時會使運算複雜度快速上升，這使得一般的解碼架構難以同時支援多種過載因子的解碼，而不符合實際需求。本論文主要研究一共有兩大主軸，分別為演算法的改良與解碼器硬體的實現。
演算法方面，我們提出一種根據個別通道的事後機率來提前刪除碼簿組合的方法，得以從第一次迭代前便降低複雜度，並且透過固定的刪減機制來降低運算的額外成本，包含運算量與記憶體的使用。
而硬體設計方面，我們選用了性能較好且較為通用的架構來設計對應的解碼器電路，其中包含了多種早停算法以及多種過載率的支援。針對多模式的支援使用了一些硬體覆用的技巧，在最高的過載模式下，運算電路的資源使用相比傳統架構減少了近65%，並且整合後的解碼器比多個單模式解碼器減少了約52%的總面積。即使在單一模式下的各項硬體性能與其他文獻相比仍不遜色，顯示本設計達成了單一模式下的性能改善與多模式的整合。

關鍵字

非正交多工存取 ； 稀疏碼多工存取 ； 訊息傳遞演算法 ； 過載因子

並列摘要

In the massive MachineType Communication (mMTC) scenario, limited spectrum and low latency and low-cost requirements are a technical bottleneck, and non-orthogonal multiple access (NOMA) has become a key technology of 5G. Among them, sparse code multiple access (SCMA) is a candidate solution that has attracted much attention recently. SCMA can use different codebooks and overload factors according to situations. However, the increase in the overload factor of the system will cause the computational complexity to rise rapidly. Conventional decoding architecture is challenging to support multiple overload factors simultaneously, which does not meet actual requirements. This thesis mainly studies two main axes, namely, the improvement of the algorithm and the realization of the decoder hardware.
In terms of algorithm, we propose a method to delete codebook combinations in advance based on the posterior probability of individual channels, reducing the complexity from before the first iteration and reduces the additional cost of calculations through a fixed reduction mechanism, including the number of calculations and memory usage.
In terms of hardware design, we chose a better-performing and more general architecture to design the corresponding decoder circuit, which includes various early stop algorithms and support for various overload factors. Some hardware reuse techniques are used for multi-mode support. In the highest overload mode, the resource usage of the arithmetic circuit is reduced by nearly 65%. The integrated decoder is compared with multiple single-mode decoders, and the total area is reduced by approximately 52%. Even in the single mode, the hardware performance is not inferior to other documents, showing that this design has achieved performance improvement in a single mode and integrates multiple modes.

並列關鍵字

Non-Orthogonal Multiple Access ； Sparse Code Multiple Access ； Message Passing Algorithm ； Overloading Factor

參考文獻

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