應用於多頻帶行動電話之全積體化0.13 μm CMOS 射頻功率放大器

現今，隨著通訊系統的快速發展及手持裝置的普及，從第二代到目前第四代行動通訊和未來第五代行動通訊發展，智慧型手機已成為生活中重要的電子產品。而由第三代合作夥伴計畫(3rd Generation Partnership Project, 3GPP)提出長期演進(Long Term Evolution, LTE)行動通訊技術發展至今，依據不同國家的選擇，使用頻帶也大不相同。為了克服第四代行動通訊資料傳輸速度的增加和頻寬的擴充，在設計行動通訊裝置中的射頻功率放大器(Radio-Frequency Power Amplifiers, RF PAs) 時，需挑戰具有高效率、高線性度和支援多模多頻(Multi-mode Multi-band)的規格。本論文主旨在於改善射頻功率放大器之效率及輸出功率，並使用互補式金屬氧化物半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程實現全積體化高效率寬頻之CMOS射頻功率放大器，採用堆疊式架構來設計功率放大器(Stacked-FET Power Amplifier)，並藉由邊耦合和堆疊耦合型功率結合變壓器來改善轉換之效率。使用0.13微米CMOS製程實現兩級射頻功率放大器，在設計上除了克服CMOS製程的低崩潰電壓和效率特性，且支持多個長期演進之頻段。使用0.13微米CMOS製程實現兩級射頻功率放大器，晶片面積為 1.26 × 1.67 mm2 ，得到的量測結果，在3.6 V供應電壓下，其在1.95 GHz時射頻功率放大器之1-dB增益壓縮點輸出功率(P1dB)為26.7 dBm，功率增益為 29.1 dB，功率附加效率(PAE)在P1dB 時為 28.9 %，最大PAE為 30.1 %，此時輸出功率為 27.36 dBm。此外，使用20-MHz LTE 16-QAM 訊號進行量測，可達到22.4 dBm 之平均輸出功率和得到19 % 的PAE。

關鍵字

射頻功率放大器；長期演進技術；功率結合變壓器；線性功率放大器；堆疊式功率放大器

並列摘要

Nowadays, with the rapid development of communication systems, as well as the popularity of handset devices evolving from the second generation to the current fourth generation of mobile communications and the future development of the fifth generation of mobile communications, smartphones have become important electronic products. Since the 3rd Generation Partnership Project (3GPP) proposed the Long Term Evolution (LTE) technology, many bands have been adopted in the LTE standard. According to different countries’ policy, the frequency bands are different. In order to overcome the increase of the LTE data rates and the expansion of the bandwidth, the design challenge of RF power amplifier is high efficiency, high linearity and multi-mode architecture in the mobile communication. This thesis proposed a way to improve the efficiency and output power of the RF PA which is implemented in Complementary Metal-Oxide-Semiconductor (CMOS) technology. The stacked-FET structure PA is used in this work and the efficiency of the RF PA is improved by the stacked coupling and edge coupling transformer. This work is implemented using 0.13 m CMOS technology, which not only overcomes CMOS transistors’ low breakdown voltage and efficiency, but also supports a lot of LTE bands. The two-stage RF PA is implemented in 0.13 μm CMOS technology. The Chip size is 1.26 × 1.67 mm2. The PA was tested under a continuous-wave (CW) input at 1.95 GHz and a supply voltage of 3.6 V. The measured small-signal gain is 29.1 dB. At the 1-dB compression point, the output power (P1dB) is 26.7 dBm with 28.9 % power-added efficiency (PAE). A maximum PAE is 30.1 % at 27.36 dBm output power. In addition, using a 20-MHz LTE 16-QAM test signal, the PA achieves 19 % PAE at an output power level of 22.4 dBm.

並列關鍵字

RF Power Amplifier (PA) ； Long Term Evolution(LTE) ； Power Combining Transformer ； Linear Power Amplifier ； Stacked-FET Power Amplifier

參考文獻

[30]S. Pornpromlikit, “CMOS RF Power Amplifier Design Approaches for Wireless Communications,” Ph.D. dissertation, University of California, San Diego, USA, 2010.

[1]“User equipment (UE) radio transmission and reception (Release 14)” 2016, 3GPP, Tech. Spec., TS 36.101 v14.0.0

[4]P.-C. Huang, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A High-Efficiency, Broadband CMOS Power Amplifier for Cognitive Radio Applications,” IEEE Trans. Microw. Theory Tech., vol. 58, no. 12, pp. 3556-3564, Dec. 2010.

[5]P. Obmann, J. Fuhrmann, K. Dufrene, J. Fritzin J. Moreira, H. Pretl, and A. Springer, “Design of a Fully Integrated Two-Stage Watt-Level Power Amplifier Using 28-nm CMOS Technology,” IEEE Trans. Microw. Theory Tech., vol. 64, no. 1, pp. 188-199, Feb. 2016.

[6]Y. Yin, X. Yu, Z. Wang, and B. Chi, “An Efficiency-Enhanced Stacked 2.4-GHz CMOS Power Amplifier With Mode Switching Scheme for WLAN Applications,” IEEE Trans. Microw. Theory Tech., vol. 63, no. 2, pp. 672-682, Feb. 2015.

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應用於多頻帶行動電話之全積體化0.13 μm CMOS 射頻功率放大器

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