本論文是以TSMC 0.18 CMOS製程,研製寬頻功率放大器和多耳蒂功率放大器,可應用於S頻段及無線區域網路、全球互通微波存取相關的頻段。論文中使用兩種電路架構。第一個電路是採兩級設計的功率放大器架構,操作頻段為1.5GHz-4GHz,使用RLC回授電路與中間極LC 階層達到寬頻匹配與功率傳輸,並設計具有偏壓式線性二極體補償電路和自我偏壓疊接電路的高線性度可靠度寬頻功率放大器。量測結果為,輸入端反射係數小於-9dB,輸出端反射係數小於-8.5dB,功率增益為7~12dB,輸出功率為13~17dBm,功率附加效率在 壓縮點為6.5~20%,其晶片面積為1.044 * 1.137 mm2。 第二個電路是使用多耳蒂架構和自適應偏壓電路的設計達到預先飽和產生最大功率輸出,操作頻率為3.5GHz,並設計具有偏壓式線性二極體補償電路和自我偏壓疊接電路的高線性度可靠度多耳蒂功率放大器。量測結果為,輸入端反射係數小於-4.8dB,輸出端反射係數小於-17dB,功率增益為6.3dB,輸出功率為12.3dBm ,功率附加效率為4.2%,其晶片面積為1.243 * 1.251 mm2。
In this thesis, we design wideband power amplifier and Doherty power amplifier for S band and Wireless Local Area Network、Worldwide Interoperability for Microwave Access systems, which are implemented in TSMC 0.18 um CMOS technology. In this thesis, we propose two circuits. In the first circuit, we propose a high linearity and reliability of CMOS wideband power amplifier, operated in the range from 1.5GHz~4GHz, with RLC feedback circuit, LC ladder, diode linearizer and Self-biased cascode technologies. Measurement results show that the input return loss is smaller than -9 dB, output return loss is smaller than -8.5 dB, power gain is 7~12 dB, output power is 13~17 dBm, power-add efficiency is 6.5~20% at 1 dB compression point, and chip size is 1.044 * 1.137 mm2. In the second circuit, we propose a high linearity and reliability of CMOS Doherty power amplifier, operated in 3.5GHz, with Doherty Structure, automatic adaptive bias control, diode linearizer and Self-biased cascode technologies. Measurement results show that the input return loss is smaller than -4.8 dB, output return loss is smaller than -17 dB, power gain is 6.3 dB, output power is 12.3 dBm, power-add efficiency is 4.2% at 1 dB compression point, and chip size is 1.243 * 1.251 mm2.