高效率IEEE802.16e編碼器設計與實作

An Efficient FPGA Implementation of IEEE 802.16e LDPC Encoder

游超元(Chao-Yuan Yu)

指導教授 ： 顧孟愷

國立臺灣大學/電機資訊學院/資訊工程學研究所/碩士(2009年)

https://doi.org/10.6342/NTU.2009.00577

摘要

在這篇論文我們實做了一個IEEE 802.16e 編碼器在FPGA上，我們利用同位元預測與修正的方式來降低在編碼過程中的資料相依性。這個編碼器可以運用在802.16e標準裡的所有碼率和碼長。此篇論文架構能有效的降低硬體複雜度和硬體面積大小並動態的在碼率1/2, 2/3, 3/4, 5/6 和碼長 576 到 2304之間切換. 其結果顯示我們所提出的編碼器架構，無論在生產率和每面積單位生產率上，都勝過一般的的編碼器。

關鍵字

低密度奇偶校驗碼 ； 802.16e

並列摘要

In this paper, a FPGA implementation of IEEE 802.16e LDPC encoder is presented. We employ parity bit prediction and correction to break up the data dependency within the encoding process. This encoder implementation can handle sixteen combinations of code rates and code lengths defined in IEEE 802.16e standards. Efficient hardware architecture reduces the complexity and area of encoder that can handle rate: 1/2, 2/3, 3/4, 5/6 and code length: 576 to 2304. Results show that the proposed architecture outperforms conventional works in terms of throughput and throughput/area ratio.

並列關鍵字

LDPC ； 802.16e

參考文獻

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