低功率低電壓連續型三角積分調變器設計

Design of Low-Power, Low-Voltage Continuous-Time Delta-Sigma Modulator

吳俊寬(Chun-Kuan Wu)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2005年)

https://doi.org/10.6342/NTU.2005.10064

摘要

近幾年，由於無線通訊系統已經變成重要的傳輸工具，而且相關的規格亦不斷的往更高的頻寬演進，因此發展高效能的相關電路技術也成了很急迫要發展的方向。
本論文將以接收端中的類比到數位轉換器 (ADC) 為一個研究主題，而由於連續型三角積分調變器(continuous-time delta-sigma ADC)可以在低電壓、低功率操作下達到高的解析度因此適合用於高效能接收機，因此本論文將以連續型三角積分調變器為研究方向。
在本論文中，是以低電壓、低功率操作為目標，並在系統的設計上達到可以切換操作模式(帶通、以及低通轉換器)，以期可以適用在多用途的通訊架構上。為了要達到低電壓、低功率的設計，本論文提供兩種設計的方法: (一)、Active gain enhancement OTA，(二)、Sliding quantizer。
此晶片使用 TSMC 0.18-μm CMOS 製程，供應電壓為1.2 V，消耗功率為1.2 mW，模擬結果為，帶通模式可以在1-MHz 的頻寬內得到 SNR值為 68 dB，並且在低通模式時可以在1.92-MHz的頻寬內得到 SNR值為 63 dB。

此晶片使用 TSMC 0.18μm CMOS 製程，供應電壓為1.2 V，消耗功率為1.2 mW，模擬結果為，帶通模式可以在1-MHz 的頻寬內得到 SNR值為 66 dB，並且在低通模式時可以在1.92-MHz的頻寬內得到 SNR值為 61 dB.

關鍵字

連續型 ； 三角積分

並列摘要

Recently, the wireless communication systems become an important tool for data link, and the specification varies day by day. Developing the high-performance circuits for wireless communication systems is an important issue.
The thesis focuses on the analog-to-digital converter in receiver design. The continuous-time delta-sigma ADC is suitable for high-performance receiver design because of the high resolution in low-voltage, and low-power operation. Therefore, we emphasize on the research of continuous-time delta-sigma ADC.
In this work, a dual-mode continuous-time delta-sigma ADC is designed and implemented for the diversity of current communication architectures. In order to achieve low-voltage, and low-power design, two new design methods are proposed: 1. Active gain enhancement OTA, 2. Sliding quantizer, and will be discussed next.
The chip is designed with a 1.2-V power supply using 0.18-μm TSMC CMOS process and the power consumption is 1.2 mW. The post-layout simulation result shows that the ADC achieves a 68-dB signal-to-noise ratio (SNR) within a 1-MHz bandwidth centered at 2-MHz in band-pass mode; and 63-dB SNR in 1.92-MHz bandwidth within the low-pass mode. Both with a sampling rate of 48 MHz.

並列關鍵字

continuou-time ； delta-sigma

參考文獻

[1] M. S. Kappes, “2.2.mW CMOS Bandpass Continuous-Time Multibit Δ-Σ ADC with 68 dB of Dynamic Range and 1-MHz Bandwidth for Wireless Applications,” IEEE Journal of Solid State Circuits, vol. 38, pp. 1098-1104, July 2003.

[2] T. Ueno and T. Itakura, “A 0.9 V 1.5 mW continuous-time Delta-Sigma modulator for WCDMA,” IEEE International Solid State Circuits Conference (ISSCC), pp. 15–19, Feb. 2004.

[3] O. Oliaei, P. Clement, and P. Gorisse, “A 5 mW Σ-Δ Modulator with 84 dB Dynamic Range for GSM/EDGE,” IEEE International Solid State Circuits Conference (ISSCC), pp. 46– 47, Feb. 2001.

[4] T. Burger and Q. Huang “A 13.5-mW 185-Msample/s Δ-Σ Modulator for UMTS/GSM Dual-Standard IF Reception,” IEEE Journal of Solid State Circuits, pp. 1868-1878, Dec. 2001

[5] L. Dörrer, F. Kuttner, P. Greco, and S. Derksen, “A 3mW 74dB SNR 2-MHz CT Σ-Δ ADC with a Tracking ADC Quantizer in 0.13-μm CMOS,” IEEE International Solid State Circuits Conference (ISSCC), pp. 492-493, Feb. 2005.