高功率與高頻氮化鋁鎵/氮化鎵電晶體研製與閘極微縮製程開發

The Fabrication of High-Power and High-Frequency AlGaN/GaN HEMTs and Development of Gate Length Reducing Process

魏旭志(Syu-Jhih Wei)

指導教授 ： 廖洺漢

國立臺灣大學/工學院/機械工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201801429

摘要

本論文使用矽基板上成長氮化鋁鎵/氮化鎵之晶圓上製作高載子遷移率電晶體，在國家奈米實驗室開發適合於氮化鎵材料的製程條件，並於I-line stepper上開發閘極微縮製程使線寬突破機台限制，來讓元件性能往高頻率及高功率邁進。
閘極微縮製程裡使用MOSFET製程常見裡自對準技術裡的概念，將MOSFET中在閘極外壁所創造的側壁空間層引入我們所設計閘極區域的內壁，利用側壁空間蝕刻製程二次打開閘極區域，同使閘極線寬因內壁的側壁空間層的沉積引發閘極區域線寬的微縮。
本研究裡面分成四個時期，前三個時期為在國家奈米實驗室開發適合於氮化鎵材料的製程條件並穩定製程條件，第四個時期開始引進閘極微縮製程並成功製作出超越I-line stepper物理極限之線寬，成功製作出操作頻率大於20GHz且崩潰電壓大於100V的高頻高功率元件。
最終希望利用矽基板上成長氮化鋁鎵/氮化鎵的低成本優點達到商業化的可能性，閘極微縮製程的開發來讓元件能在有限的製程條件下達到最佳的電性表現，在降低成本的同時也有不俗的電性表現，進一步讓矽基板上成長氮化鋁鎵/氮化鎵之晶圓結合閘極微縮製程後，使此製程技術擁有商業化的本錢。

關鍵字

氮化鎵 ； 二維電子氣 ； 高載子遷移率電晶體 ； 閘極微縮製程 ； 側壁空間蝕刻 ； 側壁空間 ； 高頻元件 ； 高功率元件

並列摘要

In this paper, we fabricate high mobility electron-transistor transistors(HEMTs) on Al-GaN/GaN on Si wafer, and develop process for GaN material at the National Nano De-vice Laboratories. We develop a gate length reducing process that allowed the scale to break through the limitation of I-line stepper and let device performance toward higher frequencies and higher power.
Using the concept of common self-alignment technology in the MOSFET process for the gate length reducing process, the spacer sidewall is created in the outer wall of the gate of the MOSFET, but we make the inner spacer sidewall of gate region and control the second spacer etching process to open gate region and let the spacer sidewall can de-posit at the inner sidewall. The gate length is reduced by the inner spacer sidewall.
The study was divided into four periods. During the first three periods, the process conditions for GaN materials were developed at the National Nano Device Laboratories and the process conditions were stabilized. In the fourth period, the gate length reducing process was introduced and successful fabricated the gate length through the limitation of I-line stepper. And the devices were fabricated with an operating frequency greater than 20 GHz and a breakdown voltage greater than 100V.
finallly, it is hoped that AlGaN/GaN on Si wafer have the low-cost advantages to arrive the commercialization possibilities. And the development of gate length reducing process to allow device to achieve the best electrical performance in the limited process conditions. While reducing costs, it also has good electrical performance. Further, after the Al-GaN/GaN on Si wafer can combine with a gate length reducing process, let this process technology can have commercialization.

並列關鍵字

GaN ； 2DEG ； HEMT ； gate length reducing process ； spacer etching ； spacer sidewall ； high frequency device ； high power device

參考文獻

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