- 學位論文
應用於第五代行動通訊系統之接收機前端電路
Receiver Front-end Circuits for 5th Generation Mobile Communication System
摘要
本研究之目標為設計應用於第五代行動通訊系統(簡稱為5G)中之射頻前端接收機電路，5G為第四代行動通訊系統(簡稱為4G)之後的延伸，以提供更高的資料傳輸率、更低延遲以及更好的用戶體驗。以射頻前端電路設計的角度而言，第五代行動通訊的核心的技術為(1)採用毫米波的頻段，提供更大的頻寬以及更快的資料傳輸速率，(2)使用相位陣列波束成型的技術，增加目標方向的增益以補償毫米波波段的路徑損耗。系統架構設計以及電路設計均為實現此通訊系統之關鍵技術，設計滿足目標系統之子電路為此研究之主要目標。 本論文的第一章會簡介相位陣列接收機在系統架構上的設計考量。首先會討論陣列收發機的基本特性，包含波束成型之原理以及陣列接收機與發射機的基本特性。本研究在系統架構上採用的是射頻相位轉移之架構，因此將會分析及討論此架構之優點以及設計挑戰。最後，計算此系統的鏈路規劃以及每個子電路的規格需求，包含增益、雜訊指數、線性度等項目。 本論文中實現兩個目標系統中的子電路，其一為低雜訊放大器，其二為降頻混頻器。在本論文的第二章中討論低雜訊放大器之設計，包含使用雙埠雜訊理論以達成雜訊指數的最佳化，以及兩個增加電路線性度的電路技巧。設計之低雜訊放大器採用TSMC 40奈米之製程，增益為19 dB，雜訊指數為3.5 dB，IP1dB為-16 dBm，功率消耗20 mW。 本論文的第三章討論降頻混頻器之設計，首先探討其規格需求，接著比較幾種典型混波器電路架構之優缺點，並且歸納且提出能滿足系統規格之電路架構，此設計採用交錯耦合電容輸入級達到高線性度以及低雜訊的特性。最後會討論該電路之設計流程以及量測結果。實現之降頻混頻器採用TSMC 90奈米之製程，降頻混頻器其電壓轉換增益為5.2 dB，功率轉換增益為-2.5 dB，雜訊指數為15.2 dB，混波器核心消耗5 mW，含緩衝器(供量測用)總功率消耗為20 mW，IP1dB為-6 dBm。 論文的第四章為此研究之結論及未來展望。
並列摘要
The goal of this research is to develop RF front-end circuits for 5th generation mobile communication system (5G). 5G is the extension of existing 4th generation mobile communication (4G) to provide higher data rate, lower latency and superior user experience. In respect to RF front-end design, the key technologies in 5G are (1) circuits operating at millimeter wave bands to provide larger data bandwidth (2) beamforming technique which utilizes multiple antennas to create a highly directional beam to compensate the path loss at millimeter wave frequencies. The main target of this research is to develop circuits which meet the system requirements in 5G. In Chapter 1, the system-level design considerations of the target transceiver are discussed. Basic characteristics and advantages of array transceiver are analyzed. Design considerations related to system architecture and link-budget are also presented. In this work, a low noise amplifier (LNA) and a downconverter are designed and implemented. In Chapter 2, the design of the LNA is discussed, including specifications, circuit architecture, analysis, design procedure and measurement result. The noise figure of the LNA is optimized based on the two-port noise theory. Two circuit techniques are used to improve the circuit linearity, and the corresponding mechanisms are analyzed. The designed LNA is implemented in TSMC 40 nm CMOS technology. It achieves 19 dB gain, 3.5 dB noise figure, -16 dBm P1dB and 20 mW power consumption. The design of the downconverter is discussed in Chapter 3, several popular downconverter circuit architectures are compared, and the architecture to meet the target requirement is proposed. The cross-coupled common-gate architecture is used to implement a high linearity and low power mixer input stage, which is necessary to satisfy the target system requirement. The designed downconverter is implemented in TSMC 90 nm CMOS technology. It achieves 5.2 dB voltage conversion gain, -2.5 dB power conversion gain, 15.2 dB noise figure, -6 dBm IP1dB. The mixer core consumes 5 mW and total power consumption (include buffer) is 20 mW. In Chapter 4, the conclusion and future work of this research are summarized.
參考文獻
延伸閱讀
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