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  • 學位論文

考慮實體資訊並應用於缺陷診斷之關鍵路徑追蹤

Physical-aware Critical Path Tracing for Defect Diagnosis

指導教授 : 李建模

摘要


這篇論文針對缺陷診斷提出一個考慮實體資訊的關鍵路徑追蹤技術,為了處理遮蔽效應、增強效應和拜占庭效應,提出了導線片段和基於導線片段之錯誤模擬的觀念。為了處理扇出重新聚合的問題,提出了反向支配者的概念。在三個ISCAS’89和ITC’99電路上,複數導線斷路缺陷的實驗證明了我們的技術有效。我們技術的平均準確率(0.87)較傳統的關鍵路徑追蹤的平均準確率(0.81)來的高,我們技術的平均解析度(3.9)也較傳統的關鍵路徑追蹤的平均解析度(5.59)來的好。

並列摘要


This thesis presents a physical-aware critical path tracing technique for defect diagnosis. To cope with masking effect, reinforcement effect, and Byzantine effect, the concept of section and section-based fault simulation are proposed. To solve fanout reconvergence problem, the idea of reverse dominator is proposed. Simulation on three ISCAS’89 and ITC’99 benchmark circuits with multiple open defects demonstrate the effectiveness of our technique. The average accuracy of our technique (0.87) is higher than traditional critical path tracing technique’s (0.81). Our technique also has better resolution (3.9) than traditional critical path tracing technique’s (5.59)

參考文獻


[Bartenstein 2001] T. Bartenstein, D. Sliwinski, D. Heaberlin, and L. Huisman, "Diagnosing combinational logic designs using the single location at-a-time (SLAT) paradigm," International Test Conference, pp. 287-287, 2001.
[Acken 1992] J. M. Acken, and S. Millman, "Fault model evolution for diagnosis: Accuracy vs precision," Custom Integrated Circuits Conference, pp. 13.4. 1-13.4. 4, 1992.
[Lee 1996] Lee, Hyung Ki, and Dong Sam Ha. "HOPE: An efficient parallel fault simulator for synchronous sequential circuits." Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 15.9 (1996): 1048-1058.
[Veneris 1999] A. Veneris, S. Venkataraman, I. N. Hajj, and W. K. Fuchs, "Multiple design error diagnosis and correction in digital VLSI circuits," VLSI Test Symposium, pp. 58-63, 1999.
[Liu 2005] Liu, Jiang Brandon, and Andreas Veneris. "Incremental fault diagnosis."Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on 24.2 (2005): 240-251..

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