一個可動態調變之晶片上網路架構設計

Design of a Dynamic Self-Reconfigurable on-Chip Interconnection Network

籃英誠(Ying-Cherng Lan)

指導教授 ： 陳少傑

國立臺灣大學/電機資訊學院/電子工程學研究所/博士(2011年)

https://doi.org/10.6342/NTU.2011.10331

摘要

本篇論文提出了一個雙向網路晶片的架構以增進晶片上資料傳輸之效能。在此雙向網路晶片中，每一傳輸通道允許動態自我改變資料的傳輸方向。而這新增的彈性可適用於大部分傳統的網路晶片並保証較好的頻寬使用率、較低的資料傳輸延遲、及較高的資料消耗率。
此雙向網路晶片使用一個新的晶片上路由器設計來達到動態調變雙向資料流的目的。資料流方向的改變由一個使用一對有限狀態機之通道方向控制演算法來決定。此有限狀態機不只提供了較高的效能，並可避免資料死結及飢餓的發生。除此之外，考慮服務質量的演算法也被整合於雙向通道控制邏輯中，以達到不同的資料服務質量需求。而藉由我們所實現的低功耗虛擬通道管理機制，雙向網路晶片可以在減少前端緩衝佇列阻塞的同時減少虛擬通道的使用量，進而在維持實作成本的同時達到高效能的目的。
最後，大量時脈精準的摸擬以人工合成資料流及實際應用資料流來評估雙向網路晶片之效能。這些結果都顯示了雙向網路晶片相較於傳統單向網路晶片具有顯著的效能優勢。而在實作上，雙向網路晶片也能有效地利用增加頻寬使用的彈性，減少了路由器上實際需要的資料緩衝暫存器用量，並達到晶片功耗及面積上的改善。

關鍵字

晶片上網路架構

並列摘要

A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this Dissertation to enhance the performance of on-chip communication while keeping the implementation cost efficient. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility can be easily fitted into most of the state-of-the-art conventional NoC designs and promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate.
The novel on-chip BiNoC router architecture is developed to support dynamic self-reconfiguration in the bidirectional traffic flow. The flow direction at each channel is decided by a channel-direction control protocol that is high-performance, free of deadlock, and free of starvation. In addition, a QoS-aware bidirectional arbitration scheme is integrated to ensure various service requirements such as best-effort, guaranteed-service, and guaranteed-throughput. Furthermore, with our proposed novel virtual-channel management, BiNoC can reduce head-of-line blocking without increasing the number of virtual-channels (VCs) thus improves performance while keeping low implementation cost.
Experimental results using both synthetic traffic patterns and E3S benchmarks verified that the proposed BiNoC architecture can significantly reduce the traffic delivery latency at all levels of traffic injection rates. Besides, the proposed QoS control mechanism can significantly improve the channel utilization for latency-sensitive traffics while keeping sufficient bandwidth for throughput-sensitive ones. Finally, it is very encouraging that the BiNoC can improve traffic delivering efficiency and achieve the goal of power and area saving by increasing bandwidth utilization flexibility and reducing the physical volume of buffer requirements.

並列關鍵字

on-chip interconnection network

參考文獻

[1] F. N. Najm, “A Survey of Power Estimation Techniques in VLSI Circuits,” IEEE Transactions on Very Large Scale Integrations Systems, vol. 2, no. 4, pp. 446-455, December 1994.

[3] L. Benini and G. De Micheli, “Networks on Chips: a New SoC Paradigm,” IEEE Transactions on Computers, vol. 35, no. 4, pp. 70-78, January 2002.

[5] W. J. Dally and B. Towles, “Route Packets, Not Wires: On-Chip Interconnection Networks,” in Proceedings of the Design Automation Conference, pp. 684-689, June 2001.

[8] R. Hegde and N. R. Shanbhag, "Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise," IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 4, pp. 379-391, August 2000.

[10] C. Constantinescu, “Trends and Challenges in VLSI Circuit Reliability,” IEEE Micro, vol. 23, no. 4, pp. 14-19, July 2003.