使用電容放大技術之鎖相迴路設計及其應用

The Design of Phase-Locked Loop Using Capacitive Multiplication Technique and Its Applications

李勝洲(Sheng-Chou Lee)

指導教授 ： 劉深淵

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2004年)

https://doi.org/10.6342/NTU.2004.10097

摘要

在今日，系統單晶片(SoC)已成為積體電路設計的主流，而鎖相迴路或是以鎖相迴路為基礎的應用對系統單晶片而言是不可或缺的。就我們所知，當互補式金氧半製程進步時，電晶體的面積也會隨著縮小，但並不包括晶片內的被動元件。低通濾波器是鎖相迴路的其中一部份，它是由電阻跟電容所組成，在過去幾年，低通濾波器總是設計在晶片外來降低晶片面積和節省生產成本。在今天，將低通濾波器整合至晶片內則是較符合系統單晶片的潮流，然而這些被動元件卻仍佔著大部份的晶片面積，假如我們想要降低這些被動元件的面積，則本論文提出的電容放大技術將可解決這個問題。
第二章會介紹鎖相迴路的基本概念，雜訊的現象也將會被提及，然後再推導出適當的設計流程。而大略的設計流程伴雜著細部參數的設定也會在這裡加以詳述。
在第三章，我們先介紹三種不同的使有電容放大技術之迴路濾波器，接著藉由行為模擬來比較跟傳統二階迴路濾波器的不同。最後，我們利用0.35微米互補式金氧半製程設計一個鎖相迴路來驗證電容放大的弁遄C
第四章提出使用第三章跟本章提出的電容放大技術之展頻時脈產生器。其中一個使用全新的電容放大技術且將迴路濾波器整合至晶片實現於0.35微米互補式金氧半製程；另一個基於第三章提出的架構實現於0.35微米互補式金氧半製程。而展頻的效果則是藉由對壓控震盪器的控制電壓調變。
在第五章，我們利用0.35微米互補式金氧半製程實現一個快速鎖定的鎖相迴路，我們將一個頻率偵測器加入鎖相迴路來達成快速鎖定的弁遄C此外，我們也提出一個新的改良式頻率偵測器，將鎖定時間大幅縮減至84%之多。

關鍵字

快速鎖定 ； 電容放大技術 ； 鎖相迴路

並列摘要

Today System-on-Chip (SoC) is a mainstream for integrated-circuit design. Phase-locked loops (PLL) or applications based on PLL are essential for SoC. As we know, when the CMOS process is improved, the transistor size becomes much smaller but not for on-chip passive components. A low-pass filter (LPF) is one of the blocks in PLL, and it is composed by resistors and capacitors. In the past years, a LPF is always designed off-chip to reduce the chip size and save production costs. Nowadays, a LPF integrated into the chip is preferred for SoC. However, these passive components will occupy large area in the chip. If we want to reduce the area occupied by these passive components, the capacitive multiplication techniques proposed in this thesis will solve this problem.
Chapter 2 will give basic ideas of phase-locked loops (PLLs). Noise performances are discussed then to derive proper design flows. A rough design flow is described along with detailed parameter setting.
In chapter 3, three kinds of loop filters with capacitive multiplication technique are introduced at first, and then the behavior simulations are taken to compare with traditional 2nd-order loop filter. Then, a PLL fabricated in CMOS 0.35-µm 1P4M process is presented to verify the capacitive multiplied function.
Chapter 4 presents the SSCGs using capacitive multiplication technique mentioned in chapter 3 and this chapter. One fabricated in CMOS 0.35-µm 2P4M process uses a new capacitive multiplication technique to integrate the LPF into chip, and the other fabricated in CMOS 0.35-µm 1P4M process is based on the architecture mentioned in chapter 3. The spread spectrum function is achieved by modulating the control voltage of the VCO.
In chapter 5, a PLL with fast locking technique is implemented in CMOS 0.35-µm 2P4M process. The proposed PLL achieves fast locking function by a frequency detector added into the PLL. In addition, we propose a new modified FD which can reduce the locking time at most by about 84%.

並列關鍵字

capacitive multiplication technique ； fast locking ； phase locked loop

參考文獻

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