三維積體電路負偏溫度不穩定效應之模擬流程與電路分析

Simulation Flow and Circuit Analysis of NBTI Effects on 3D Integrated Circuits

林政宏(Cheng-Hong Lin)

指導教授 ： 盧奕璋

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2010年)

https://doi.org/10.6342/NTU.2010.01357

摘要

由於製程的演進，負偏溫度不穩定效應(Negative bias temperature instability, NBTI)逐漸成為可靠性問題中重要的效應。先前的論文中已經有提出用來預測臨界電壓漂移程度以及電路效能退化的分析模型，該模型是由許多環境參數所組成的數學函式。對於臨界電壓漂移的預測，必須使用這些分析模型計算，藉此預測遭受NBTI衝擊之後效能退化的程度。對於電路效能的預測，除了可以使用分析模型來完整估計退化程度，也可以使用SPICE來輔助計算。在本論文中，我們使用先前論文提出的臨界電壓預測公式來計算ΔVth，再利用HSPICE以及NBTI影響後的電路次模型來計算電路效能的退化情形。
由於3DIC具有高密度以及垂直堆疊的特性，因此有提昇電路效能以及降低成本等優點，但是卻因為高功率密度的特性使得散熱困難以及高環境溫度成為其致命缺點。NBTI效應對於環境溫度是非常敏感的，先前的論文有提到保護關鍵邏輯閘(Critical Gates, CGs)可以有效降低NBTI效應的衝擊。在本論文中，我們將這兩個觀念引入至三維積體電路中，並且驗證了將關鍵邏輯閘放置在三維晶片中低溫的位置可以有效降低NBTI效應的影響。我們也以此觀念建立了四核心三維處理器晶片平面圖，並跟其他一般的平面圖比較。我們使用Hotspot對它們進行穩態溫度模擬，並且使用HSPICE模擬以及比較它們受到NBTI效應導致的退化程度。我們並且使用平面晶片佈局軟體Encounter 來完成三維積體電路佈局圖，最後提出本篇論文所使用的引入NBTI效應的三維積體電路實現流程。

關鍵字

負偏溫度不穩定效應 ； 效能退化 ； 溫度 ； 關鍵邏輯閘 ； 三維積體電路

並列摘要

With CMOS technology scaled into 65nm and 45nm node, the NBTI (negative bias temperature instability) effect has become a major reliability problem in modern circuit systems. In order to predict the threshold voltage shift and circuit performance degradation caused by NBTI, several analytical models have been proposed, and these models are functions of numerous condition parameters. To predict threshold voltage shift, NBTI can be calculated using the analytic model. However, the circuit performance degradation cannot be estimated using the analytic model alone, but through circuit simulations, such as SPICE. In this thesis, we predict ΔVth using predictive models proposed by other papers and utilize NBTI sub-circuit model for PMOS to calculate circuit performance degradation using HSPICE. The 3DIC (three-dimensional integral circuits) has features of high transistor density and vertically stacked dies, so it has the advantage such as enhancing circuit performance and reducing cost. However, 3DIC has the potential problem of high power density, which might cause difficulty in heat conduction and thus high chip temperature. As the NBTI effect is very sensitive to local temperature, protecting Critical Gates (CGs) can thus effectively reduce the impact of NBTI. In this work, we introduce two new concepts to 3DIC design and implementation. Firstly, we propose that in 3DIC, the CGs should be placed on low temperature dies in order to mitigate NBTI effect. Then we create a floorplan of 3D quad-core four chip system based on this concept and compare to other common floorplans. We use Hotspot to simulate steady state temperature. Finally, we propose an NBTI-aware 3DIC implement flow, which can be used to implement 3DIC layout that has less impacts from NBTI.

並列關鍵字

NBTI ； performance degradation ； thermal ； critical gates ； 3DIC

參考文獻

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