三維積體電路之電源供應網路的模型建置流程與其自動化

現在半導體產業界中，晶片製程為了降低成本而一直走向縮小化的趨勢。而這個趨勢也已經被摩爾定律規範出來。不過現有的晶片製程的微影蝕刻技術已經逐漸達到物理的極限。而為了要繼續邁向縮小化的目標，必須要發展一些解決的方式。藉由垂直晶片堆疊的三維積體電路提供了有效的解決方式，可以達到高密度，高效能，以及做到不同功能晶片的系統整合。而在三維積體電路中所使用的堆疊技術中，直通矽晶孔柱，因擁有較短的電氣長度，故可以達成較高效能的傳輸，是目前最備受矚目的技術。不過，三維積體電路的研發有許多需要解決的問題。其中，電源供應網路的電源完整性設計是其中一個重要的議題，而在三維電源供應的雜訊耦合更為複雜。要能對在電源供應網路的雜訊傳遞進行探討以及設計，準確的建構包含直通矽晶孔柱在內的完整三維積體電路的電源供應網路等效電路模型是必要的。直通矽晶孔柱在走向高密度的製程的趨勢是極有可能的。故在本篇會特別探討一對直通矽晶孔柱在極近距離之下的電氣特性。傳統的直通矽晶孔柱模型無法適用於極近距離的情況，本篇則藉由保角轉換的方式，提出一個改良型的模型而成功進行修正。而當直通矽晶孔柱結合晶片內部電源供應網路時，供應網路的金屬繞線會和半導體的矽表面產生耦合，這堆疊部分的效應需要被考慮。我們也會提出一個適用於考慮這些耦合特性的效果的等效模型。在提出模型建構的流程之後，為了能運用到較大範圍的三維積體電路結構, 我們建立了電路模型的自動化程序。藉由自動化程序的幫助，大範圍結構的等效電路模型可以立刻產生，經有此電路我們可以做一些結構上的分析與應用．最後搭配一些程序上的設定，我們可以對等效電路的效果及實用性做出一個應用上的規格，方便我們做分析。日後，可以幫助進行電源供應網路的相關設計。

關鍵字

三維積體電路；直通矽晶孔柱；電源供應網路；電源完整性；保角轉換；等效電路模型；自動化程序

並列摘要

In semiconductor industry nowadays, shrinking the transistor size has been the trend of chip process to reduce the cost. However, since the technique of lithography in chip process has almost reached the physical limit, some solutions are needed to keep following Moore’s law. Three-dimensional integrated circuit (3-D IC) provides an promising one of the solutions which can reach high density, high performance, and system integration of heterogeneous functionality by vertically stacking the chips. Many stacking technologies have been developed, in which through-silicon via is the most promising one due to its shorter electrical length, and as a result, higher performance of transmission. Nevertheless, there are still many problems needed to be solved in 3-D IC design, where power integrity is one of the most important issues. In order to study and suppress the coupling noise in power delivery network, it is necessary to construct an accurate equivalent circuit model for full power delivery system in 3-D IC. Since high-density process of TSV is the trend, electrical behavior of fine-pitch TSVs will be discussed. Compared to the conventional TSV model, which is not suitable when two TSVs are close, an improved model for fine-pitch TSVs by using conformal mapping is proposed in this thesis. Besides, noticeable coupling between metal in power/ground grids and the TSVs inside the silicon substrate will occur as TSVs are connected to the power/ground grids. This effect is also considered based on the TSV coupling node insertion method (TSV-CNIM) in the equivalent circuit model. Finally, automatic program for generating SPICE netlists of the 3-D IC has been developed in attempt to analyze large-scale 3-D IC structures. Using this automatic program, equivalent circuit model of the PDN in 3-D IC can be generated instantaneously, and the electrical behavior of the PDN can be characterized and designed can be made more efficiently.

並列關鍵字

Three-dimensional integrated circuit ； through-silicon via ； power delivery network ； power integrity ； conformal mapping ； equivalent circuit model ； automatic programing

參考文獻

[1] S. Borkar, “Design Challenges of Technology Scaling,” IEEE Micro, vol. 19, no. 4, Jul.-Aug. 1999, pp. 23-29.

[2] G. Moore, "Cramming more components onto integrated circuits," Electron., vol. 38, no. 8, pp. 114-117, 19 Apr. 1965.

[3] A. Chris, “Fifty Years of Moore’s Law,” IEEE Trans. Semiconductor Manufacturing, vol. 24, no. 2, pp. 202, May 2011.

[4] F. Schwierz, "Graphene transistors," Nature Nanotech, 5, pp. 487-496, 2010.

[5] R. R. Tummala, ”SOP: what is it and why? a new microsystem-integration technology paradigm-Moore’s law for system integration of miniaturized convergent systems of the next decade,” IEEE T-AdvP, pp. 241-249, May 2004.

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三維積體電路之電源供應網路的模型建置流程與其自動化

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