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  • 學位論文

三維積體電路電源供應網路的高效率時域模型建置方法

An Efficient Time-Domain Power-Delivery-Network Modeling Methodology for Three-Dimensional Integrated Circuit (3-D IC)

指導教授 : 吳宗霖

摘要


為了滿足日漸提高的高性能消費性電子產品的需求,半導體產業在過去四十年來有飛躍性的進步,摩爾定律也一直被奉為圭臬而持續遵循。不過,由於今日電晶體大小已相當接近物理的極限,想要繼續縮小電晶體尺寸同時維持低成本已變得相當困難,造成此一定律變得難以遵循。為了突破此一困境,最近幾年許多可能的解決方案紛紛被提出。其中使用直通矽晶孔柱的三維積體電路由於有較低的功耗、較小的電阻壓降和較高的傳輸速度,因而成為最有可能繼續摩爾定律甚至超越摩爾定律的解決方案。 雖然使用直通矽晶孔柱的三維積體電路被寄予厚望且發展蓬勃,此一技術仍有許多挑戰及困難有待克服,像是電氣特性議題、熱流傳導議題、成本議題...等。在電氣特性議題中,電源供應網路的設計是相當關鍵性的問題。在沒有適當設計的情況下,一個系統可能會因而效能降低甚至失去應有的功能。而想要適當的設計它,一個正確且有效率的電源供應網路模型是必要的。因此,本文重視如何建立正確的三維積體電路中電源供應網路模型以及如何改善其模擬效率,並同時提出適當的解決方案。 對於正確性這一點,本文提出一個階梯狀電路的建置流程,用此一電路來正確地描述三維積體電路中電源供應網路之集膚效應。和傳統常用的方法相比,此一電路不但頻域模擬正確性較高而且可以直接進行時域的模擬,也不會有任何潛在的被動性和因果性的電路問題,因此使用此電路分析電源供應網路也會更有效率。更重要的是,此一電路模型可以由結構的物理尺寸及材料特性直接獲得,不須額外使用電氣特性萃取的軟體,因此對於自動化電路建置流程有很大的幫助。 為了改善所建立的電源供應網路模型之模擬效率,本文提出一套簡化模型的方法來化簡此一相當複雜的電源供應網路模型。此一方法是依據基本的串、並聯及單位元的概念建立。運用此化簡方法可以顯著地減少模型中所需的電路元件數,因此模擬時間可以縮短。更重要的是,簡化的模型在時域和頻域的正確性依舊相當高。

並列摘要


With the demand of the high-performance consumer electronics, the semiconductor industry has progressed dramatically in the past 40 years, and Moore’s law has guided the development of the entire semiconductor industry. However, as the size of transistors approaches the physical limit, this law is much more difficult to be tenable due to the difficulties in shrinking the gate length at the same time remaining low-cost. To overcome this obstacle, many possible solutions have been proposed. Among them, three-dimensional integrated circuit (3-D IC) with through silicon vias (TSVs) has the advantages of lower power consumption, smaller IR drop, and higher transmission rate capability. Therefore, it is very likely to become the major method to continue Moore’s law or to become “more than Moore”. Although 3-D IC with TSVs has great potential, there are still many challenges needed to be overcome such as electrical-property issues, thermal issues, cost issue, and so on. Among electrical-property issues, the design of power delivery network (PDN) is one of the most critical problems. A system can degrade or even malfunction without a good design of PDN. To facilitate it, a not only accurate but also efficient model of PDN is essential. Therefore, this thesis focuses on how to establish an accurate model for PDN in 3-D IC and how to improve the simulation efficiency. In terms of accuracy, a ladder-circuit-model-constructing methodology is proposed to accurately characterize the non-negligible skin effect of PDN in the 3-D IC. Compared with the conventional skin effect model, the accuracy of this model is much higher. In addition, this model can be directly used in time-domain simulation without any potential passivity and causality problems, which can also make the analysis of the PDN more efficient. Most importantly, this model can be constructed from its physical dimensions and material properties without any help of electrical-parameter extraction tools, which makes the automation of the methodology straightforward. To improve the efficiency of the established model of PDN in 3-D IC, a simplification methodology for the rather complex PDN model in 3-D IC, based on the basic serial formulas, shunt formulas, and unit-cell concept, is proposed. This simplification method can significantly reduce the number of the circuit elements in the model, which makes the simulation time much shorter, but the accuracy is still good enough both in frequency domain and in time domain.

參考文獻


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[5] International Roadmap for Semiconductors (ITRS), 2012 Update. http://www.itrs.net.

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