應用於低頻感測系統之兩階電壓控制震盪器連續時間三角積分類比前端電路設計

Design of Voltage-Controlled-Oscillator-Based Continuous-Time Delta-Sigma Analog Front-End Circuit for Low Frequency Sensing Applications

陳翰群(Han-Chun Chen)

指導教授 ： 林宗賢

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2018年)

https://doi.org/10.6342/NTU201803204

摘要

感測器系統扮演著人類和機器之間的橋樑，隨著物聯網和人工智慧的演進感測器系統也越來越重要。此外，隨著半導體工業的進步，我們也希望能夠將龐大的電路系統實現在單一晶片中，本論文著重探討應用於此系統的類比前端電路設計。此電路的主要任務為將振幅極小且低頻的感測器信號直接轉換為數位訊號，並希望在電壓和功率消耗的限制下，有足夠的頻寬和訊噪比。傳統的感測器介面電路係由一個低雜訊放大器加上一個類比數位轉換器所組成，不論在功率及面積方面都較沒效率，在電路的設計上也比較複雜，為了解決上述這些問題，本篇採用兩組電壓控制震盪器來實現兩階的連續時間三角積分調變器，為一個有類比前端特性的連續時間類比數位轉換器。
本論文對我們所設計的連續時間三角積分轉換器做了實作及量測，此電路實作於台積電一百八十奈米製程。這個作品將第一級積分過的訊號藉由第二級由電壓控制震盪器所構成的量化器做量化，由於量化器本身具有一階三角積分調變的特性，故整個迴路會有兩階的三角積分調變，且此量化器的數位輸出為一個經動態單元匹配後的訊號可以提升電容式數位類比轉換器的線性度，故不需要再加上動態權重平均電路，而能有較大的頻寬。此電路之核心晶片面積為零點一九毫米平方，本晶片工作於一百萬赫茲的取樣頻率下並使用一點二伏特的供給電壓，在六千赫茲的頻寬下的訊雜扭曲比為六十二點五分貝，整個電路的功率消耗為五十三點八微瓦，質量指標為一百四十三點七分貝。經過量測證實此晶片能符合低頻感測前端電路的需求，並在能量效率及晶片面積上有很好的表現。

關鍵字

低頻前端電路 ； 電壓控制震盪器 ； 三角積分調變器

並列摘要

Sensor systems are becoming more and more important with the progress of IOT and AI. Besides, we hope to integrate whole sensors system which includes sensor interface circuit and digital processor in one chip. Therefore, this thesis focuses on the power and area efficient analog front end (AFE) design. Conventional sensor interface circuit consists of a low noise amplifier and an analog to digital converter (ADC). It is inefficient on both power consumption and area, and also complex to design. To solve the above problem, this thesis uses two voltage control oscillator (VCO) based circuits as the integrator and quantizer to implement the 2nd-order continuous time delta-sigma modulator (CTDSM), merging an ADC with the AFE.
This thesis implements and measures the CTDSM in TSMC 180 nm CMOS process. This work uses a VCO and a counter as an integrator. Furthermore, we add another VCO with frequency-to-digital converter as a quantizer. Due to the first-order noise shaping characteristic of the second-stage. The whole loop shows second-order noise shaping. The second-stage quantizes the signal as a digital thermometer code with dynamic element matching (DEM), we do not need the dynamic weighted averaging (DWA). The core area of the chip is 0.19 mm2. This chip using sampling frequency at 1 MHz, with supply voltage of 1.2 V. This chip achieves the signal-to-noise-and-distortion-ratio of 62.5 dB. The power consumption of this chip is 52.4 μW, and the FoMs of the work is 143.7 dB. This chip meets bio-AFE requirement and is outstanding on power consumption and chip area.

並列關鍵字

Analog front end ； voltage control oscillator ； delta-sigma modulation

參考文獻

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