應用於無線區域網路CMOS低雜訊放大器、功率放大器之設計及壓控震盪器之量測

Design of CMOS Low Noise Amplifier, Power Amplifier and Measurement of Voltage Controlled Oscillator for WLAN

張昱信(Yu-Hsin Chang)

指導教授 ： 黃恆盛

國立臺北科技大學/機電學院/自動化科技研究所/碩士(2005年)

摘要

基於2.4 GHz之操作頻率，本論文的前兩部分分別是低雜訊放大器之設計和壓控震盪器的量測，均是使用TSMC 0.25μm 1P5M CMOS的製程，第三部份是利用UMC 0.18μm 1P6M CMOS製程來研製功率放大器，以上設計均依循802.11b WLAN規範。
第一部份是增益可調式低雜訊放大器之設計，此架構第二級利用單個共源極放大器取代原本的串疊共汲極放大器來提高1dB功率壓縮點，有效增加線性度。此低雜訊放大器具有增益17.323∼-0.8dB，2.055dB雜訊指數，1dB增益壓縮點為-14dBm，而工作電壓為1.5V。
第二部分是壓控振盪器之量測，工作電壓為1.2V，模擬的可調頻率範圍在2.363∼2.557GHz，相位雜訊為-124.7dBc/Hz@1MHz，量測結果的可調頻範圍為 2.257GHz∼2.377GHz，相位雜訊為-78.4dBC/Hz@1MHz，功率消耗為5.06mW。
第三部份是差動式self-biased Cascode class E功率放大器之設計，此架構第一級操作偏壓於class AB當做驅動級使用，第二級利用self-biased架構改善了傳統串疊組態（Cascode topology）的高工作電壓和高功率損耗的缺點並且增加了功率增加效率(Power added efficiency)，而整個電路設計成差動式的架構，使工作電壓可以在更低的情況下達到WLAN的規格。在layout上使用了bound wire的模擬和UMC所提供的pad以增加量測的準確度。此功率放大器在工作電壓為2.2V情形下，功率增加效率可達42.62%。

關鍵字

串疊組態 ； 功率增加效率

並列摘要

Based on 2.4 GHz operation frequency, the first two parts of this thesis are the design of low noise amplifier and the measurement of voltage controlled oscillator. Both of them use TSMC standard 0.25μm CMOS technology. The third one uses UMC standard 0.18μm CMOS technology for power amplifier. They are all designed in compliance with 802.11b WLAN.
Starting from the design of a variable gain low noise amplifier, the second stage of the amplifier uses common source to replace original cascade common drain to increase 1 dB compression point and enhance linearity. The proposed LNA chip achieves the performance as following：17.323∼-0.8 dB for power gain, 2.055 dB for noise figure, the 1dB compression point at -14 dBm, and 1.5 V for supply voltage.
The second is the measurement of voltage controlled oscillator with 1.2 V supply voltage. The simulation results show frequency range among 2.363~2.557 GHz, -124.6dBc/Hz@1MHz phase noise. The test results show frequency range among 2.257~2.377 GHz, -78.4dBc/Hz@1MHz phase noise, 5.06 mW power consumption.
The third is the design of differential self-biased Cascode class E power amplifier. The first stage of the amplifier operates bias at class AB for drive stage. The second stage uses self-biased topology to improve typical Cascade topology’s high supply voltage, high power consumption defects, and increase power added efficiency. The circuit is designed as differential topology to achieve WLAN specification at lower supply voltage. The layout uses bound wire simulation and pad provided by UMC to increase the accuracy of test. This PA chip operated at 2.2V can achieve 42.62% power added efficiency.

並列關鍵字

Cascode topology ； Power added efficiency

參考文獻

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