用於頻率合成器中傳輸線電感、壓控振盪器與除頻器之設計和研究

Design and Implementation of Transmission line Inductors, VCO and ILFD used in Frequency Synthesizer

陳宗彥(Tsung-Yen Chen)

指導教授 ： 林佑昇

國立暨南國際大學/科技學院/電機工程學系/碩士(2009年)

https://doi.org/10.6837/NCNU.2009.00266

摘要

本論文以用於頻率合成器中之傳輸線電感、壓控振盪器與除頻器為研究目標，研究主題分成三部分：
第一部份為用於頻率合成器中之傳輸線電感，我們設計使用CMOS製程中較底層之金屬來鋪墊在所設計的傳輸線電感底下，減少電感在使用時對silicon substrate所造成的substrate loss效應，使該傳輸線電感可應用於高頻電路如壓控振盪器與除頻器。我們使用UMC 90um CMOS製程技術設計傳輸線電感，實驗結果顯示在高頻部分，有使用底層金屬來替傳輸線電感加以遮蔽比起沒有的在Q-factor的表現上提升71.69%，使傳輸線電感可應用在高頻部分。
第二部份為壓控振盪器，我們使用台積電0.18mm CMOS製程技術設計並實現了兩個K-band Voltage Control Oscillators (VCOs)。其中一個1 MHz相位雜訊為-104.31 dBc/Hz、工作頻率為17.879GHz 到 20.094GHz 當調變電壓為 0 到 1.3V。 其核心消耗功率僅為 10.582 mW。 壓控振盪器的 figure of merit (FOM) 為-180.09 dBc/Hz。另一個壓控振盪器的1 MHz相位雜訊為-98.64 dBc/Hz、工作頻率為24.058GHz 到 26.042GHz 當調變電壓為 0 到 1.5V。 其核心消耗功率為 13.725 mW。 壓控振盪器的 figure of merit (FOM) 為-174.9 dBc/Hz。
第三部份為使用台積電0.13mm CMOS製程技術設計並實現的兩個注入鎖定除頻器(ILFD)，分別為除2及除3。為了提高可除頻範圍在除2注入鎖定除頻器上使用shunt-peaking技術並利用可變電容之可調容值來滿足提高可除頻範圍的目的。除2注入鎖定除頻器最大可除頻率為64.76 GHz，核心消耗功率為3.394 mW、可除範圍則為10.144 GHz (從54.612GHz 到 64.756 GHz)以及最小到注入訊號功率為-60dBm依然可除。另一個注入鎖定除頻器則以差動注入的方式達到除3的目的並配合利用可變電容之可調容值來提高可除頻範圍該注入鎖定除頻器可除範圍為3.132 GHz (從38.231GHz到41.363 GHz) 、核心消耗功率為4.56 mW。

關鍵字

傳輸線電感 ； 壓控振盪器 ； 注入鎖定除頻器

並列摘要

This thesis aim is the design and implementation of transmission line inductors, VCO and ILFD used in frequency synthesizer. The research subject can be divided into three parts：
In first part, we design some transmission line inductors with metal ground shielding to reduce substrate loss when the inductors used in high frequency environment. The transmission line inductors were implemented by UMC 90nm CMOS technology and the measurement result shows the Q-factor of transmission line with ground shielding can be 71.69% higher than which without shield. The transmission line inductors can be used in high frequency environment.
In the second part, we design two voltage control oscillators (VCOs) implemented by TSMC 0.18mm CMOS technology. One VCO achieves phase noise of -104.31 dBc/Hz at 1 MHz offset and operates the frequencies from 17.879GHz to 20.094GHz with a tuning voltage from 0 to 1.3V. The power consumption of this VCO core is only 10.582 mW. The figure-of merit (FOM) of the VCO is -180.09 dBc/Hz. Another one achieves phase noise of -98.64 dBc/Hz at 1 MHz offset and operates the frequencies from 24.058GHz to 26.042GHz with a tuning voltage from 0 to 1.5V. The power consumption of this VCO core is only 13.725 mW. The figure-of merit (FOM) of the VCO is -174.9 dBc/Hz.
The last part, two Injection-Lock Frequency Dividers implemented by TSMC 0.13mm technology are presented. One is a low-power 64.76-GHz (V-band) injection-locked frequency-divider (ILFD) by using Shunt-Peaking technique and the other is a V-band direct Injection-Locked divide-by-three Frequency Divider. In the first divider to reduce power consumption and enhance locking range, a peaking inductor TL3 is connected to the internal node to resonate with the parasitic capacitor by transistors M1, M2 and M3 at input frequency. Therefore, the locking range will be enhanced by the internal power can be increased due to the increase of the impedance at the internal node. This ILFD architecture also features a very low input capacitance; thus, high operating frequency of 64.76 GHz can be achieved. This ILFD consumes 3.394 mW with locking range of 10.144 GHz (54.612~64.756 GHz) 17% and excellent sensitivity of -60dBm. The other divider is to divide-by-three ILFD, the injection part in this circuit is designed by two PMOS and two differential signals input in two PMOS gate point. On the other hand, the circuit core has one module of voltage control varactors for frequency tuning. In order to tune circuit free-running and makes it Wide-Bandwidth, the operating voltage of varactors can be changed. This ILFD consumes 4.56 mW with locking range of 3.132 GHz (38.231~41.363 GHz).

並列關鍵字

transmission line inductors ； VCO ； injection-lock frequency divider ； ILFD ； K-band ； V-band ； shunt-peaking

參考文獻

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