使用增加式資料加權平均器之三階多位元連續時間三角積分調變器

在本論文中提出了一個符合窄頻應用的三階多位元的連續時間三角積分調變器，在此調變器中使用了增加式資料加權平均器，其可將數位到類比轉換過程所產生的誤差作一階的雜訊抑制，並且可以將因訊號功率小所產生的許多單頻雜訊移出訊號頻帶之外。此三角積分調變器使用台積電0.18微米互補式金氧半製程所實現，其使用24MHz的取樣頻率在100kHz的頻寬下可以得到77dB的訊號雜訊比和80dB的動態範圍，使用1.8伏的供應電源時，只需要消耗4.5毫瓦的功率。此連續時間三角積分調變器適合使用於無線接收機系統之中。在本論文中另外也提出一個低電壓低功率的運算轉導放大器，此電路是根據電流鏡運算轉導放大器作為基礎，為了改善低電壓增益的問題，使用了幾個技巧加以改良，首先，並聯部分的電流鏡電流，用來降低輸出偏壓電流以增加輸出阻抗，而且並聯的電流可以拿來作第二輸入級使用，另外，基極端可以當作輸入使用增加轉導，最後，使用AB類輸出級可以大幅提高增益，此運算轉導放大器也是使用台積電0.18微米互補式金氧半製程所實現，在驅動16.8pF的電容負載時，其30kHz的電壓增益為55dB，單一增益頻率為26.3MHz而相位邊際則是52.4度，使用0.9伏的供應電源時，其只需要消耗280微瓦的功率。

關鍵字

多位元；連續時間；增加式資料加權平均器

並列摘要

Designed for a narrow-band application, a third-order multi-bit continuous-time delta-sigma modulator is presented in this thesis. In the modulator, the incremental data weighted averaging algorithm is employed. The IDWA can achieve first-order DAC noise shaping and move the signal dependent tone out of the signal band. This delta-sigma modulator is implemented in the TSMC 0.18-μm COMS process. The proposed modulator achieves a 77-dB peak SNR with a 100-kHz bandwidth at a 24-MHz sampling rate and has an 80-dB dynamic range. The implemented modulator dissipates only 4.5 mW from a 1.8-V supply. The proposed continuous-time delta-sigma modulator is suitable for wireless zero-IF or low-IF receiver systems. A low-voltage low-power CMOS OTA is also introduced in this thesis. The proposed circuit is based on the current-mirror topology. To circumvent the low-gain problem of a CMOTA, several design techniques are employed. First, the output impedance is increased by reducing the bias currents of the output branches, which is realized by shunting partial mirror currents away. These shunt currents are then reused to realize the second input stage. In addition, body terminals are utilized as inputs to augment the transconductance. Finally, the class-AB output stage further enhances the gain. The proposed OTA is implemented in the TSMC 0.18-μm COMS process. With a load 16.8 pF, the proposed OTA achieves a 55-dB gain at 30 kHz with a unity-gain frequency of 26.3 MHz and the phase margin is 52.4°. The implemented OTA dissipates only 280 μW from a 0.9-V supply.

並列關鍵字

multi-bit ； continuous-time ； incremental data weighted averaging

參考文獻

[1] L. Breems and J. H. Huijsing, Continuous-Time Sigma-Delta Modulationfor A/D Conversion in Radio Receivers. Boston, MA: Kluwer, 2001.

[3] S. Rabii and B. A. Wooley, The Design of Low-Voltage, Low-Power Sigma Delta Modulator. Kluwer academic publisher, 1999.

[5] R. J. Van De Plassche, “A monolithic 14-bit D/A converter,” IEEE J. Solid-State Circuits, vol. SC-14, no. 3, pp. 552-556, June 1979.

[6] L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” IEEE J. Solid-State Circuits, vol. SC-24, no. 2, pp. 267-273, April 1989.

[7] R. Baird and T. Fiez, “Linearity enhancement of multibit ΣΔ A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 753–762, Dec. 1995.

國際替代計量

使用增加式資料加權平均器之三階多位元連續時間三角積分調變器

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