使用時域雜訊耦合的循序漸進-增量式積分三角類比數位轉換器之設計與分析

Design and Analysis of a SAR-ISDM ADC with Time-Domain Noise Coupling

張哲維(Che-Wei Chang)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202203505

摘要

本論文提出一個單通道兩階混合式類比數位轉換器用於高功率效率的資料轉換，由循序漸進式類比數位轉換器為粗分轉換及時域增量式積分三角調變器為細分轉換所組成。以增量式積分三角調變器為細分轉換中，在採用門控延遲振盪器作為積分器達到一階雜訊移頻的基礎上，提出了一個一階時域雜訊耦合技術來實現有效的二階雜訊移頻。此外，也提出了一個雜訊耦合路徑。本論文對增量式積分三角調變器轉換的時間餘裕進行了分析以及對壓控振盪器和具有分離電壓時間轉換器的門控延遲振盪器進行了比較。
本晶片使用台積電四十奈米互補式金屬氧化物半導體製程實現，在取樣頻率為一千五百萬得到65.29分貝的訊號雜訊失真比、79.45分貝的無雜散動態範圍，並且功耗為2.72毫瓦。Schreier品質因素為159.7分貝，Walden品質因素為121 fJ/conversion-step。

關鍵字

類比數位轉換器 ； 循序漸進式類比數位轉換器 ； 增量式積分三角調變器 ； 高解析度 ； 雜訊耦合 ； 時間數位轉換器

並列摘要

In this thesis, a single-channel two-step hybrid analog-to-digital converter (ADC), consisting of a successive approximation register (SAR) ADC and a time-domain incremental sigma-delta modulator (ISDM) for coarse and fine conversion, is proposed for power-efficient data conversion. On the basis of a gated-delay oscillator (GDO) as an integrator employed to achieve the first-order noise shaping in the fine ISDM conversion, a first-order time-domain noise coupling (TDNC) technique is proposed to realize the effective second-order noise shaping. In addition, the proposed noise-coupled path is also presented. The analysis of the time margin of the ISDM conversion and the comparison of a voltage-controlled oscillator (VCO) and the GDO with a separated voltage-to-time converter (VTC) are presented in this thesis.
The proposed ADC fabricated in TSMC 40-nm CMOS technology achieves a signal-to-noise and distortion ratio (SNDR) of 65.29 dB and a spurious free dynamic range (SFDR) of 79.45 dB at a 15-MS/s sampling rate, and the power consumption is 2.72 mW. The Schreier figure of merit (FoM) is 159.7 dB, and the Walden FoM is 121 fJ/conversion-step.

並列關鍵字

Analog-to-digital converter (ADC) ； successive approximation register (SAR) ADC ； incremental sigma-delta modulator (ISDM) ； high resolution ； noise coupling ； time-to-digital converter (TDC)

參考文獻

[1] Y.-C. Chan, “Design and Analysis of a SAR-ISDM ADC with Gated-delay Oscillator Integrator,” Master’s thesis, National Taiwan University, Taipei, Taiwan, Jan. 2020.

[2] S. Pavan, R. Schreier, and G. C. Temes, Understanding Delta-Sigma Data Converters. Wiley-IEEE Press, second ed., 2017.

[3] J. Markus, J. Silva, and G. Temes, “Theory and Applications of Incremental ΔΣ Converters,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, pp. 678–690, Apr. 2004.

[4] S.-E. Hsieh and C.-C. Hsieh, “A 0.4V 13b 270kS/S SAR-ISDM ADC with an Opamp-Less Time-Domain Integrator,” in IEEE ISSCC Dig. Tech. Papers, pp. 240–242, Feb. 2018.

[5] S.-E. Hsieh and C.-C. Hsieh, “A 0.4-V 13-bit 270-kS/s SAR-ISDM ADC With Opamp-Less Time-Domain Integrator,” IEEE J. Solid-State Circuits, vol. 54, pp. 1648–1656, June 2019.